2017年9月5日（火）に、浙江大学のProf. Chen Zhuoをお招きして、高速メモリの階層間をまたがる最適設計に関する講演会をしていただきました。
From System to PHY: Optimization for modern memory
With modern memory continuing contributing significant power, it is highly desirable to lower supply voltage for the memory, thereby effectively limiting its power consumption. However, due to the ever-growing system complexity (host and memory) and performance demands, in tradition, designers are very conservative with memory supply voltage and scale at a much slower pace compared with core and GPU. Now, with the popularity of HBM and HMC, memory may become even more power hungry. Designers have to be more aggressive with memory’s voltage scaling, but such a goal is not easy to meet without hurting performance and signal integrity. In particular, the challenges arise from two perspectives:
-System. A comprehensive memory system starts from host controller through off-chip channel to memory. Due to the increasing interactions between host and memory, the entire system needs to be investigated altogether to avoid over-pessimism.
-Model. Model needs to account for both accuracy and efficiency. In order to enable a system-level design exploration, it is crucial to model the power delivery impacts on memory performance, which are dynamic and happen within the entire system from passive interconnects to active circuits.
In this talk, we will cover the aforementioned challenges and present our recent researches on modern memory’s power and performance from a system perspective. At system level, we will discuss how to incorporate front-end SoC architecture to back-end models to enable the system level simulations. At model level, we will go through back-end modeling details covering all the possible coupling effects between power delivery and memory signal, from transmitter, channel to receiver. We will then present experimental results on necessary trade-offs to enable our design exploration and early-stage validation.
