Mr.  Shumpei Morita presented his paper in the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC 2018) held in Jeju Island, Korea.

Morita’s talk was about the analysis of the circuit degradation. The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads, and thus path delay degradation is strongly dependent on each use case. In this paper, we propose a subset simulation (SS) framework that efficiently and accurately finds the worst case workload and the failure probability covering various workloads. In the proposed method, workloads that yield worst aged delay are efficiently generated by the NBTI-aware Markov chain Monte Carlo method. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to the naive Monte Carlo method. From the result of the SS, feasible workload that gives worst aged delay is obtained.

  • Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Efficient Exploration of Worst Case Workload and Timing Degradation under NBTI,” Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC) (Jeju Island, Korea), pp.631-636, Jan. 2018.
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