参加学会2010年

2010年03月18日~03月19日,TAU 2010(ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) )在美国加州旧金山的Marriott Fisherman’s Wharf举行,B4(当时)片山同学此次学会中进行了研究发表.

  • Kentaro Katayama, Takanori Date, Hiroyuki Ochi, and Takashi Sato: “Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis,” in Proc. of ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) (San Francisco, CA), pp.121-126, Mar. 2010.

2010年03月22日~03月24日,ISQED(The International Symposium on Quality Electronic Design) 2010在美国加州圣何塞(San Jose)的DoubleTree Hotel举行,隶属东京工业大学益研究室的D2(当时)萩原先生,M2(当时)高橋同学进行了各自的研究発表。

  • Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, and Takashi Sato: “Linear Time Calculation of State-Dependent Power Distribution Network Capacitance,” International Symposium on Quality Electrical Design (ISQED) (San Jose, CA), pp.75-80, Mar. 2010.
  • Takanori Date, Shiho Hagiwara, Kazuya Masu, and Takashi Sato: “Robust Importance Sampling for Efficient SRAM Yield Analysis,” International Symposium on Quality Electrical Design (ISQED) (San Jose, CA), pp.15-21, Mar. 2010.

2010年04月19日〜04月22日,IEEE VTS’10(28th VLSI Test Symposium)在美国加州圣克鲁斯(Santa Cruz)的Seascape Beach Resort举行,上薗研究员发表了自己的研究成果。

  • Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, and Takashi Sato: “Path Clustering for Adaptive Test,” IEEE VLSI test symposium (VTS) (Santa Cruz, CA), pp.15-20, Apr. 2010.

2010年05月30日~06月02日に,ISCAS(The IEEE International Symposium on Circuits and Systems) 2010在法国巴黎的Disney’s Hotel New York举行,佐藤教授,上薗研究员分别发表了研究成果.

  • Takashi Sato, Takumi Uezono, Noriaki Nakayama, and Kazuya Masu: “Decomposition of Drain-Current Variation into Gain-Factor and Threshold Voltage Variations,” IEEE International Symposium on Circuits and Systems (ISCAS) (Paris, France), pp.1053-1056, May 2010.
  • Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, and Takashi Sato: “Small Delay and Area Overhead Process Parameter Estimation Through Path-Delay Inequalities,” IEEE International Symposium on Circuits and Systems (ISCAS) (Paris, France), pp.3553-3556, May 2010.

2010年07月04日~07月07日,ITC-CSCC 2010(The 25th International Technical Conference on Circuits/Systems, Computers and Communications)在泰国芭堤雅(タイ・パタヤ)的Ambassador City Jomtien举行,D1(当时)今川同学进行了研究発表。

  • Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, and Takashi Sato: “A Tool Chain for Generating SEU-Vulnerability Map for Coarse-Grained Reconfigurable Architecture,” in Proc. of 26th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2010) (Pattaya, Thailand), pp.420-423, July 2010.

2010年09月27日~09月29日,SoCC 2010(23rd IEEE International SoC Conference)在美国内华达州的拉斯维加斯(Las Vegas)的Bally’s Las Vegas举行,D1(当时)今川同学进行了研究发表。

  • Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, and Takashi Sato: “A Routing Architecture Exploration for Coarse-Grained Reconfigurable Architecture with Automated SEU-Tolerance Evaluation,” in Proc. of IEEE International SOC Conference (SOCC) (Nevada, USA), pp.248-253, Sep. 2010.

2010年09月02日~09月03日,DA Symposium 2010-“系统LSI设计技术与DA”在爱知县丰桥市的ホテル日航豊橋举行,M1(当时)的宮川同学做了研究发表。

  • 宮川 哲朗, 山長 功, 越智 裕之, 佐藤 高史: “重点的サンプリングを用いたランダムウォークによる線形回路解析の高速化”, 情報処理学会DAシンポジウム2010 (於 愛知県豊橋市 ホテル日航豊橋), 2010年9月.
  • 増田 弘生, 佐方 剛, 佐藤 高史, 橋本 昌宜, 古川 且洋, 田中 正和, 山中 俊輝, 金本 俊幾: “RTNを考慮した回路特性ばらつき解析方法の検討”, 情報処理学会DAシンポジウム2010 (於 愛知県豊橋市 ホテル日航豊橋), 2010年9月.

2010年11月07日~11月13日,ICCAD(The International Conference on Computer-Aided Design) 2010在美国加州圣何塞(San Jose)的DoubleTree Hotel举行,M1(当时)片山同学进行了研究发表。另外,同时举行的研讨会(workshop)IEEE/ACM Workshop on Compact Variability Modeling (CVM) 中,上薗研究员做了研究发表。

  • Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis,” in Proc. of ACM/IEEE International Conference on Computer-aided Design (ICCAD) (San Jose, CA), pp.703-708, Nov. 2010.
  • Takumi Uezono, Tadamichi Kozaki, Hiroyuki Ochi, and Takashi Sato: “A Transistor-Array for Parallel BTI-Effects Measurements,” in Proc. of Workshop on Variability Modeling and Characterization (VMC), Nov. 2010.

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