DATE 2013

Posted on Monday March 25th, 2013 by admin

On March 20th, Mr. Imagawa and Mr. Rákossy presented their recent works at Design, Automation & Test in Europe (DATE) 2013, which was held in Grenoble, France.

  • Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, and Hiroyuki Ochi: “Hot-Swapping Architecture with Back-Biased Testing for Mitigation of Permanent Faults in Functional Unit Array,” Design, Automation & Test in Europe (DATE) (Grenoble, France), Mar. 2013.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “A Cost-Effective Selective TMR for Heterogeneous Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis,” Design, Automation & Test in Europe (DATE) (Grenoble, France), Mar. 2013.
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    IEICE General Conference　2013

    Posted on Friday March 22nd, 2013 by admin

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    ISQED 2013

    Posted on Thursday March 14th, 2013 by admin

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    (日本語) 環境電磁工学研究会 (EMCJ)

    Posted on Wednesday March 13th, 2013 by admin

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    VLD Excellent Student Author Award for ASP-DAC

    Posted on Thursday March 7th, 2013 by admin

    On March 4th, at Okinawa, Mr. Shintani received the VLD Excellent Student Author Award for ASP-DAC. This award is given to the student who presented an influencial paper in ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC). The prize paper is as follows.

    • Michihiro Shintani and Takashi Sato, “An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC) (Pacifico Yokohama, Yokohama, Japan), Jan. 2013, pp.614-619.

    On the same day, he gave the following commemorative lecture.

    • ［］ Michihiro Shintani and Takashi Sato, “An Adaptive Current-Threshold Determination for IDDQ Testing Based on BayesianProcess Parameter Estimation,” Technical report of VLD (Nippon seinen-kan, Okinawa), vol. 112, no. 451, VLD2012-152, p. 91, March 2013.
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    (日本語) VLSI設計技術研究会 (VLD)

    Posted on Thursday March 7th, 2013 by admin

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    Laboratory tour for 3rd year undergraduate students (2nd day)

    Posted on Friday February 22nd, 2013 by admin

    We held a laboratory tour for 3rd year undergraduate students.

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    Laboratory tour for 3rd year undergraduate students (1st day)

    Posted on Thursday February 21st, 2013 by admin

    We held a laboratory tour for 3rd year undergraduate students. This tour will be also held tomorrow. For more information, please see http://www.pass.cce.i.kyoto-u.ac.jp/?page_id=1428.

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    Paper accepted for GLSVLSI2013

    Posted on Monday February 18th, 2013 by ts

    The following paper is accepted for presentation at GLSVLSI2013, which will be held on May 2-4 in Paris, France.

    • Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato, ”Fast and Memory-Efficient GPU Implementations of Krylov Subspace Methods for Efficient Power Grid Analysis,” Great Lakes Symposium on VLSI (GLSVLSI) (Paris, France), May. 2013 (to appear).
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    IEEE Kansai Section Student Paper Awards

    Posted on Wednesday February 13th, 2013 by admin

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