Processor Architecture and Systems Synthesis Laboratory

Professor Dennis Sylvester visited our group on June 12.
He gave a seminar talk at the Research Bldg. No.8, Kyoto University.

Speaker: Prof. Dennis Sylvester (University of Michigan, Ann Arbor)
　　　　　 http://web.eecs.umich.edu/~dennis/

Title: Ultra Low Power System Design Challenges and Solutions

Abstract: This talk describes a design approach that focuses on
system-level energy minimization to achieve nanowatt-level complete
microsystems. Starting with proper technology selection, the approach
systematically targets power minimization in critical design building
blocks including timers, memories, processors, and interface circuits.
Near-threshold circuits are a key element in designing such ultra-low
power blocks and the state of the art in ultra-low power design of
these components will be reviewed, while areas requiring further
reductions will be highlighted. Finally, the feasibility of major
(order of magnitude) advances in low power circuits to enable energy
autonomous microsystems will be briefly discussed, including
technology-circuit co-optimization and accelerator-based design.

Bio: Dennis Sylvester received a PhD from the University of
California, Berkeley and is Professor of Electrical Engineering and
Computer Science at the University of Michigan, Ann Arbor. He has
published over 350 articles along with one book and several book
chapters and holds 16 US patents. His research interests include the
design of millimeter-scale computing systems and energy efficient
near-threshold computing for a range of applications. He is
co-founder of Ambiq Micro, a fabless semiconductor company developing
ultra-low power mixed-signal solutions for compact wireless devices.
He is a Fellow of the IEEE.

Professor Anupam Chattopadhyay visited our group on May 24.
He gave a seminar talk at the Building 3, Faculty of Engineering, Kyoto University.

Speaker: Prof. Anupam Chattopadhyay

Subject: Future-proof IP Design for Heterogeneous MPSoC

Summary: Heterogeneous Multi-Processor System-on-Chip has become commonplace in diverse application domains to balance the conflicting　performance constraints. Within the context of constituent IPs of a heterogeneous MPSoC, we will present two major challenges. Both the challenges are linked with fundamental advances of semiconductor technology and its approaching roadblock at deep submicron　technology. First, in the /What /challenge we will discuss about the IPs that one can design for catering to a growing clientele for a long　time and still guarantee efficiency. Examples from wireless receiver and cryptography will be discussed in this part. In the second part, the /How /challenge will deal with the ability to design these IPs by considering multiple performance constraints simultaneously. The　proposed solutions are based on the Synopsys Processor Designer toolsuite, making these readily available to wide range of users.

Speaker bios: Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by CoWare (now part of Synopsys). He further developed several high-level optimizations and verification flow for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. He has published more than 40 technical papers, authored one book and several book-chapters in the above research areas.

Prof. Dr.-Ing. Chattopadhyay spent over 3 years in various engineering and research positions at industry. In his most recent industrial position he was serving as a Member of Consulting Staff at CoWare, India, where he was responsible for enhancing the quality and capability of a high-level processor synthesis toolsuite.

In 2010, Prof. Dr.-Ing. Chattopadhyay joined RWTH Aachen University as an assistant professor in the UMIC research cluster. He is heading the research group of MPSoC Architectures.

On April 25, 2013, We have a welcome party for senior students and farewell party for an assistant professor at “Hyakumanben Sharaku”.

Sorry, this entry is only available in 中文 and 日本語.

Sorry, this entry is only available in 中文 and 日本語.