Tag Archives: VLD

(日本語) VLSI設計技術研究会2020年3月

Posted on Wednesday April 1st, 2020 by ts

Sorry, this entry is only available in 日本語.

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IEICE VLD Excellent Student Author Award for ASP-DAC 2020

Posted on Sunday March 29th, 2020 by ts
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(日本語) 2019年5月VLD研究会

Posted on Tuesday May 21st, 2019 by ts
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Excellent student author award for ASP-DAC2019

Posted on Friday March 15th, 2019 by ts
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(日本語) 2016年3月VLD研究会

Posted on Monday March 7th, 2016 by hiromoto

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(日本語) 2015年3月VLD研究会

Posted on Friday March 6th, 2015 by hiromoto

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VLD Excellent Student Author Award for ASP-DAC

Posted on Thursday March 7th, 2013 by admin

On March 4th, at Okinawa, Mr. Shintani received the VLD Excellent Student Author Award for ASP-DAC. This award is given to the student who presented an influencial paper in ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC). The prize paper … Continue reading →

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(日本語) VLSI設計技術研究会 (VLD)

Posted on Thursday March 7th, 2013 by admin

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Design Gaia 2012

Posted on Tuesday November 27th, 2012 by admin

Zhi Li (master course 2nd degree) has made a presentation about his work at Design Gaia 2012. Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Accurate I/O Buffer Impedance Self-Adjustment using Vth and Temperature Sensors,” IEICE Technical Report, Vol.112, No.320, … Continue reading →

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参加学会2011年

Posted on Thursday March 29th, 2012 by admin

2011年03月14日～03月16日に，アメリカ合衆国・カリフォルニア州Santa Clara，Hyatt Regency HotelにてISQED(The International Symposium on Quality Electronic Design) Symposium 2011が開催され，M1(当時)の湯浅君が発表を行いました． Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs,” in Proc. of International Symposium on Quality Electrical … Continue reading →

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