Tag Archives: Journal

一篇文章被收录于 IEICE Transactions

Posted on 01/06/14 Monday by ts

以下文章被收录于IEICE Transactions on Electronics. Shiho Hagiwara, Takanori Date, Kazuya Masu, and Takashi Sato, “Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis,” to appear in IEICE Transactions on Electronics.

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(日本語) IEICE 論文誌への論文掲載

Posted on 01/01/14 Wednesday by ts

電子情報通信学会 英文論文誌 IEICE Transactions on Electronics 中，刊载了以下文章。 Koh Yamanaga, Shiho Hagiwara, Ryo Takahashi, Kazuya Masu, and Takashi Sato, “State-Dependence of On-Chip Power Distribution Network Capacitance,” IEICE Transactions on Electronics, Vol.E97-C, No.1, pp.77-84, Jan. 2014.

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(日本語) IEEE 論文誌 (IEEE Transactions on Electron Devices) への論文掲載

Posted on 11/01/13 Friday by ts

在 IEEE Transactions on Electron Devices 上刊登了论文. J.B. Velamala, K.B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, and Y. Cao, “Compact Modeling of Statistical BTI Under Trapping/Detrapping,”  IEEE Transactions on Electron Devices, vol.60, no.11, pp.3645-3654, Nov. 2013. (doi: 10.1109/TED.2013.2281986) URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6612719&isnumber=6637023 … Continue reading →

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(日本語) IEICE Transactions on Electronics への採録決定

Posted on 10/25/13 Friday by ts

以下论文被 IEICE Transactions on Electronics 采用了. Koh Yamanaga, Shiho Hagiwara, Ryo Takahashi, Kazuya Masu, and Takashi Sato, “State-Dependence of On-Chip Power Distribution Network Capacitance: Measurement and Analysis, to appear in IEICE Transactions on Electronics, Vol.E97-C, No.1, Jan. 2014.

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IEICE 論文誌への論文掲載

Posted on 04/26/13 Friday by ts

电子情报通信学会的英文论文集 IEICE Transactions on Electronics, IEICE Transactions on Information and Systems 中，被采用的论文为以下几篇： Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato, “Parallel acceleration scheme for Monte Carlo based SSTA using generalized STA processing element,” IEICE Transactions on Electronics, Vol.E96-C, No.4, … Continue reading →

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(日本語) IEICE 論文誌への論文掲載

Posted on 12/31/12 Monday by admin

对不起，此内容只适用于English和日本語。

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IEICE 论文发表

Posted on 12/12/12 Wednesday by admin

以下2篇论文被IEICE电子通信期刊采用 : Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,” IEICE Transactions on Electronics, Apr. 2013 (to appear). Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “A … Continue reading →

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IEICE Transactions on Information and Systems论文采用

Posted on 10/24/12 Wednesday by admin

新谷同学（博士课程2年级）的以下研究成果被IEICE Transactions on Information and Systems决定采用。 Michihiro Shintani and Takashi Sato, “Device-Parameter Estimation Through IDDQ Signatures,” IEICE Transactions on Information and Systems. (to appear)

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两篇研究论文在IEICE Trans. Fundamentals, Special Section on “VLSI Design and CAD Algorithms”上被刊登

Posted on 07/29/12 Sunday by admin

修士二年级的粟野同学和川島同学的研究成果被IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on “VLSI Design and CAD Algorithms” (December 2012 Issue) 刊登。 Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Bayesian Estimation of Multi-Trap RTN Parameters using Markov Chain … Continue reading →

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IEICE Trans. Fundamentals, Special Section on “VLSI Design and CAD Algorithms” への採録決定

Posted on 07/29/12 Sunday by admin

修士二年级的粟野同学和川島同学的研究成果被IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on “VLSI Design and CAD Algorithms” (December 2012 Issue) 刊登。 Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Bayesian Estimation of Multi-Trap RTN Parameters using Markov Chain … Continue reading →

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