Tag Archives: ISQED

(日本語) ISQED 2017

Posted on 03/28/17 Tuesday by hiromoto

对不起，此内容只适用于English和日本語。

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(日本語) ISQED 2016

Posted on 03/23/16 Wednesday by hiromoto

对不起，此内容只适用于日本語。

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ISQED2014

Posted on 03/09/14 Sunday by ts

对不起，此内容只适用于日本語。

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ISQED 2013

Posted on 03/14/13 Thursday by admin

2013年3月4日～6日，International Symposium on Quality Electronic Design (ISQED) 2013在美国加利福尼亚州圣克拉拉市举行，本研究室今川和粟野学长做了自己的研究发表。 Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “High-Speed DFG-Level SEU Vulnerability Analysis for Applying Selective TMR to Resource-Constrained CGRA,” International Symposium on Quality Electrical Design (ISQED) (Santa Clara, CA), March … Continue reading →

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ISQED2013论文采用

Posted on 11/27/12 Tuesday by admin

以下2篇论文将刊登在ISQED2013（2013年3月） Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Multi-Trap RTN Parameter Extraction Based on Bayesian Inference,” International Symposium on Quality Electrical Design (ISQED) (Santa Clara, CA), Mar. 2013 (to appear). Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “High-Speed … Continue reading →

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ISQED2012 (03/19-03/21)

Posted on 05/01/12 Tuesday by admin

2012年3月19日〜21日，ISQED (The International Symposium on Quality Electronic Design) Symposium 2012 在美利坚合众国加利福尼亚州Santa Clara，Techmart Center举行。佐藤教授做了以下的研究发表。 Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, and Hiroyuki Ochi: “Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices,” in Proc. of International Symposium … Continue reading →

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2011年 所有参加的学会

Posted on 03/29/12 Thursday by admin

2011年03月14日～03月16日，ISQED(The International Symposium on Quality Electronic Design) Symposium 2011在美利坚合众国加利福尼亚州Santa Clara，Hyatt Regency Hotel举行，M1(当時)湯浅同学进行了研究成果发表。 Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs,” in Proc. of International Symposium on Quality Electrical … Continue reading →

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参加学会2010年

Posted on 03/29/12 Thursday by admin

2010年03月18日～03月19日，TAU 2010(ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) )在美国加州旧金山的Marriott Fisherman’s Wharf举行，B4(当时)片山同学此次学会中进行了研究发表． Kentaro Katayama, Takanori Date, Hiroyuki Ochi, and Takashi Sato: “Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis,” in … Continue reading →

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