Tag Archives: DAC

DAC2020

Posted on Tuesday July 28th, 2020 by ts

Dan, a graduate of our group presented his research at the 57th ACM/IEEE Design Automation Conference (DAC) 2020 held from July 20 to July 24, 2020 (presentation date: July 25). In addition to DAC being the top conference in integrated … Continue reading →

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DAC2020: paper accepted

Posted on Thursday February 13th, 2020 by ts

The following paper has been accepted for presentation in Design Automation Conference 2020. The paper presentation from our group in the DAC conference is five years in a row. Akira Dan, Riu Shimizu, Takeshi Nishikawa, Song Bian and Takashi Sato, … Continue reading →

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DAC2019

Posted on Tuesday June 25th, 2019 by ts
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Our paper has been accepted for presentation in DAC2019 Las Vegas!

Posted on Thursday February 7th, 2019 by ts

The following paper has been accepted for presentation in DAC2019（ACM/IEEE Design Automation Conference 2019） (acceptance rate 24.8%=202/815). Conguratulations!! Song Bian, Masayuki Hiromoto, and Takashi Sato, “Filianore: Better multiplier architectures for LWE-based post-quantum key exchange,” in Proc. ACM/IEEE Design Automation Conference … Continue reading →

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(日本語) DAC2018

Posted on Tuesday July 3rd, 2018 by ts
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A paper presented at DAC2017

Posted on Wednesday June 28th, 2017 by hiromoto

Mr. Song Bian presented his paper in Design Automation Conference (DAC) 2017 held in Austin, Tx. Song’s presentation was on creating learning-based STA libraries for characterizing aging-induced device variations. Traditional approach to the accurate characterization of aging (specifically negative bias … Continue reading →

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Student paper accepted for presentation in DAC 2017

Posted on Monday February 13th, 2017 by hiromoto

The following paper has been accepted for presentation in DAC 2017 (ACM/IEEE Design Automation Conference). Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations,” in Proc. of ACM/IEEE Design Automation … Continue reading →

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Article on our DAC2016 paper

Posted on Thursday June 23rd, 2016 by ts

Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.

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A paper presented at DAC2016

Posted on Wednesday June 15th, 2016 by ts

Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx. His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations … Continue reading →

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Student paper accepted for presentation in DAC 2016

Posted on Thursday February 18th, 2016 by hiromoto

The following paper has been accepted for presentation in DAC 2016 (ACM/IEEE Design Automation Conference). Hiromitsu Awano and Takashi Sato, “Efficient Transistor-level Timing Yield Estimation via Line Sampling,” ACM/IEEE Design Automation Conference (DAC), accepted for presentation, Jun 2016. (Austin, TX)

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