Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx.
His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations considering a large number of variables have been successfully conducted in a practical time. Experimental results indicated the analysis containing more than 1000 variable becomes possible and approximately 300x acceleration has been achieved. The proposed method is particularly useful to analyze highly parallelized processors, such as GPU, designed using an advanced technology node.
DAC is the largest and most prestigious conference in this area (acceptance ratio: 22.6% = 152/674).
A large number of attendees gather to the conference which is held in conjunction with a huge exhibition and collocated workshops.
- Hiromitsu Awano and Takashi Sato, “Efficient transistor-level timing yield estimation via line sampling,” in Proc. Design automation conference (DAC), paper 69.3, June 2016.
