The 40th PARTHENON Workshop was hold on September 29, 2014 in Yoshida Campus, Kyoto University. In the conference, Takashi Imagawa (D3) and Tsuyoshi Okazaki (M2) made presentations. In addition, emeritus Professor Yukihiro Nakamura, made a special speech entitled “The 22-year history of PARTHENON Technical Society and its future.”
Imagawa’s talk is about the time-overlapping method to improve the soft-error tolerance of coarse-grained reconfigurable architecture. Conventional time-redundancy methods compare all output data and take the majority. This results in the same process being executed every time. The proposed method terminates execution once the error is found in the processed result. Using this method, the probability of error correction for the processed result is expected to be as low as virtually impossible. In this presentation, experimental implementation has shown that the proposed method is 2.5 times more reliable than typical time-redundancy methods.
Okazakaki made a presentation on the topic of automated measurement of device characteristics using FPGA. Transistors manufactured in recent technology generations tend to suffer a greater level of characteristic variation (CV), which is known to be one of the major threats to the reliability of modern VLSI circuits. Since CV is represented as a probability distribution, a large amount of devices has to be measured. In his presentation, a new setup has been proposed, which automates CV measurements on a large number of devices. By designing a dedicated circuitry on an FPGA board for each measurement scenario, hundreds of thousands of devices can be efficiently measured. By measuring the distribution of minimum operating voltage of flip-flops, it is confirmed that predictions and improvement propositions developed in the simulation process are also effective in the actual design.
The following articles are only available in Japanese:
- 今川 隆司, 廣本 正之, 越智 裕之, 佐藤 高史:
“粗粒度再構成可能アーキテクチャ向けの省メモリな耐ソフトエラー時間多重化手法”, 第40回パルテノン研究会, pp.37-44, 2014年9月. - 岡崎 剛, 川島 潤也, 廣本 正之, 佐藤 高史:
“フリップフロップの最小動作電圧計測のためのFPGAを用いた自動測定環境の構築”, 第40回パルテノン研究会, pp.1-6, 2014年9月.
