Paper Published on IEEE Transactions on Device and Materials Reliability

The following article has been published on IEEE Transactions on Device and Materials Reliability.

Hiromitsu Awano, Masayuki Hiromoto and Takashi Sato, “BTIarray: A Time-overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability,” IEEE Transactions on Device and Materials Reliability, vol.14, no.3, pp.833-843, Sept. 2014. (doi:10.1109/TDMR.2014.2327164)

VLSI circuits were thought to be strong against wear-out failures. However, recent technology generations have reduced the thickness of the gate oxide to the extent of several atoms. An extremely subtle degradation in circuit element is now amplified to the extent that it can no longer be overlooked. The core problem in researching the circuit degradation issue is the measurement time. Circuit degrades in a time span of several years, so even measurements under an accelerated environment take hours to several days. Furthermore, since transistors have became such tiny, each transistor varies a lot in its characteristics with respect to the others. Hence, instead of only measuring the degradation characteristics of one transistor, hundreds to thousands of transistor devices have to be measured to achieve adequacy. In this paper, a parallel structure has been proposed to measure the Bias Temperature Instability (BTI) degradation effect of transistors. The proposed design is able to measure hundreds of transistors concurrently and thus reduce the measurement time to that of a single transistor. A test circuit was fabricated on 65nm process technology, and it was experimentally confirmed that the variation in BTI degradation is inversely proportional to the transistor channel area. The proposed design make it possible to statistically measure and model degradations characteristics, and is one of the foundation for long-term reliability of VLSI circuits.

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