Paper Published on IEICE Transactions on Information an Systems

The following paper has been published on IEICE Transactions on Information and Systems.
IDDQ test is a way of measuring manufacturing faults in chips by measuring the leakage current while the chip is in its quiescent state (i.e., when all inputs to the chip are hold constant and there are no internal switchings inside the chip). However, recently, due to the increasingly large characteristic variation of transistors, it is hard to decide if the large leakage current is generated from device variation or the chip’s internal fault. To solve this problem, this paper proposes a design method that estimates the characteristic variation on each chip. Following this, the range of leakage current due to characteristic variation is calculated from the result of previous estimation. Based on this calculation, every single chip will then have a its own standard that can be used to accurately decide weather it is a faulty chip. The reliability of circuits can be greatly improved by applying this method.

  • Michihiro Shintani and Takashi Sato, “IDDQ Outlier Screening through Two-phase Approach: Clustering-based Filtering and Estimation-based Current-threshold Determination,” IEICE Transactions on Information and Systems, Vol.E97-D, No.8, pp.2095-2104.
This entry was posted in Publication and tagged , . Bookmark the permalink.