Journal papers published on Trans. IEICE

The following papers are published on Trans. IEICE.

  • Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato, “Parallel acceleration scheme for Monte Carlo based SSTA using generalized STA processing element,” IEICE Transactions on Electronics, Vol.E96-C, No.4, pp.473-481, April, 2013. (Kyoto University repository)
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato, “A cost-effective selective TMR for coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis,” IEICE Transactions on Electronics, Vol.E96-C, No.4, pp.454-462, April, 2013. (Kyoto University repository)
  • Michihiro Shintani and Takashi Sato, “Device-parameter estimation through IDDQ signatures,” IEICE Transactions on Information and Systems, Vol.E96-D, No.2, pp.303-313, February, 2013. (Kyoto University repository)
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