Monthly Archives: July 2017

Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Posted on Wednesday July 19th, 2017 by hiromoto

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation … Continue reading →

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SSDM 2017: paper accepted

Posted on Friday July 14th, 2017 by hiromoto

The following paper has been accepted for oral presentation in International Conference on Solid State Devices and Materials (SSDM), which will be held during September 19-22, 2017. Michihiro Shintani, Kazunori Kuribara, Yasuhiro Ogasahara, Masayuki Hiromoto, and Takashi Sato: “A Design-Analysis … Continue reading →

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