Monthly Archives: November 2016

ATS 2016

Posted on Monday November 28th, 2016 by hiromoto

Mr. Bian presented his paper at Asian Test Symposium (ATS 2016) held in International Conference Center Hiroshima, Japan. Song’s talk was on the mitigation of NBTI degradation in processors. Integrated circuits suffer from the so called aging effect, represented by … Continue reading →

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(日本語) 電気学会 電子デバイス・半導体電力変換合同研究会 学生奨励賞を受賞

Posted on Thursday November 24th, 2016 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) VMC 2016

Posted on Friday November 18th, 2016 by hiromoto

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WiPDA 2016

Posted on Wednesday November 16th, 2016 by hiromoto

Dr. Shintani and Mr. Oishi presented their papers at the IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA) held in Fayetteville, AR, USA. Dr. Shintani’s presentation was about a circuit simulation model for V-groove SiC power MOSFET with … Continue reading →

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(日本語) 電気学会 電子デバイス・半導体電力変換 合同研究会

Posted on Tuesday November 15th, 2016 by hiromoto

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Student paper accepted for presentation in DATE 2017

Posted on Tuesday November 15th, 2016 by hiromoto

The following paper has been accepted for presentation in DATE 2017 (Design, Automation & Test in Europe). The acceptance rate for regular papers is 24%. Song Bian, Masayuki Hiromoto, and Takashi Sato: “Scam: Secured Content Addressable Memory Based on Homomorphic … Continue reading →

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