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Daily Archives: Wednesday February 17th, 2016
Student paper accepted for presentation in GLSVLSI 2016
A paper is accepted for presentation in GLSVLSI 2016 (Boston, MA). Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation,” Great Lakes Symposium on VLSI (GLSVLSI) (Boston, MA), … Continue reading
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ISQED2016: paper accepted
The following paper has been accepted for presentation in ISQED 2016. Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, and Takashi Sato: “Nonlinear Delay-Table Approach for Full-Chip NBTI Degradation Prediction,” in Proc. of International Symposium on Quality Electronic Design (ISQED) … Continue reading
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Students’ papers accepted for presentation in TAU 2016
The following papers are accepted for publication in TAU workshop 2016, congratulations! Hiromitsu Awano and Takashi Sato: “Efficient Transistor-Level Timing Yield Estimation via Line Sampling,” in Proc. of ACM/IEEE International Workshop on Timing Issues (TAU) (Santa Rosa, CA), Mar. 2016 … Continue reading
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