2013年7月4日～5日, 在函館举办的电子情报通信学会 集成电路研究会（ICD）上， 本研究室的M2 藤田君作了研究发表(7月5日)．
藤田君本次发表是关于为了实现超低功耗电路的设计而进行的低电压仿真中电路误动作的原因分析。在实际应用中，可实现便携设备，传感器网络和蓄电池驱动的设备的低功耗化设计以及增长设备的可操作时间。
在本研究中，通过对电路的输出信号的观测，展示了电路中低电压运行时的错误原因的分析，并对每一个问题的对策进行简单化处理。
2013年7月1日～3日，在韩国丽水举办的ITC-CSCC 2013上，本研究室的今川君和張君做了各自的研究发表。
今川君的发表的是关于存储器中数据读取操作的低功耗电路设计的内容。为了实现低功耗传感器网络或者文化财产等的宝贵数据的长期存储，长时间甚至能够长久存储的设备的开发成为了一个重要课题。
张君的发表是关于提出电路中延迟时间的高精度计算的内容。本研究是为了实现便携设备等要求能够在低电压下长时间工作的特性而进行的。因此本研究的实际应用也被寄予了期待。
2013年6月12日(周三)に，密西根大学安娜堡分校的Dennis Sylvester教授来到本研究室交流访问，并在
京都大学综合研究8号馆做了“关于传感器等低功耗电路的设计”的主题演讲。
演讲者: Prof. Dennis Sylvester (University of Michigan, Ann Arbor)
http://web.eecs.umich.edu/~dennis/
演讲题目: Ultra Low Power System Design Challenges and Solutions
演讲概要: This talk describes a design approach that focuses on system-level energy minimization to achieve nanowatt-level complete microsystems. Starting with proper technology selection, the approach systematically targets power minimization in critical design building blocks including timers, memories, processors, and interface circuits. Near-threshold circuits are a key element in designing such ultra-low power blocks and the state of the art in ultra-low power design of these components will be reviewed, while areas requiring further reductions will be highlighted. Finally, the feasibility of major (order of magnitude) advances in low power circuits to enable energy autonomous microsystems will be briefly discussed, including technology-circuit co-optimization and accelerator-based design.
演讲者简历: Dennis Sylvester received a PhD from the University of California, Berkeley and is Professor of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor. He has published over 350 articles along with one book and several book chapters and holds 16 US patents. His research interests include the design of millimeter-scale computing systems and energy efficient near-threshold computing for a range of applications. He is
co-founder of Ambiq Micro, a fabless semiconductor company developing ultra-low power mixed-signal solutions for compact wireless devices. He is a Fellow of the IEEE.
2013年5月24日(周五)，亚琛工业大学（RWTH Aachen University) 的Anupam Chattopadhyay教授来到本研究室进行交流并在京都大学工学部3号馆进行了演讲。
演讲人: Prof. Anupam Chattopadhyay
题目: Future-proof IP Design for Heterogeneous MPSoC
演讲概要: Heterogeneous Multi-Processor System-on-Chip has become commonplace in diverse application domains to balance the conflicting performance constraints. Within the context of constituent IPs of a heterogeneous MPSoC, we will present two major challenges. Both the challenges are linked with fundamental advances of semiconductor technology and its approaching roadblock at deep submicron technology. First, in the /What /challenge we will discuss about the IPs that one can design for catering to a growing clientele for a long time and still guarantee efficiency. Examples from wireless receiver and cryptography will be discussed in this part. In the second part, the /How /challenge will deal with the ability to design these IPs by considering multiple performance constraints simultaneously. The proposed solutions are based on the Synopsys Processor Designer toolsuite, making these readily available to wide range of users.
演讲者建立: Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by CoWare (now part of Synopsys). He further developed several high-level optimizations and verification flow for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. He has published more than 40 technical papers, authored one book and several book-chapters in the above research areas.
Prof. Dr.-Ing. Chattopadhyay spent over 3 years in various engineering and research positions at industry. In his most recent industrial position he was serving as a Member of Consulting Staff at CoWare, India, where he was responsible for enhancing the quality and capability of a high-level processor synthesis toolsuite.
In 2010, Prof. Dr.-Ing. Chattopadhyay joined RWTH Aachen University as an assistant professor in the UMIC research cluster. He is heading the research group of MPSoC Architectures.
平成25年4月25日(周四)19時～，在百万遍 しゃらく（饭店名）举办了B4的欢迎会和筒井助教的欢送会。
高垣 勇登同学，羅 丹同学，山本 高裕同学自本年度4月开始光荣的成为了藤高史研究室的一员。
另外，筒井助教从本年度5月1日始， 赴北海道大学 情報科学研究科 多媒体网络专攻（メディアネットワーク専攻）出任副教授。
在此，再次向筒井教员为本研究室付出的辛劳和汗水表示衷心的感谢。
2013年5月2日至3日，法国巴黎召开的GLSVLSI 2013上，本研森下先生（D1）做了研究成果演讲。
（发表日为5月2日，口头发表采用率21% (=51/238), 其中regular presentation采用率为13% (=30/238)）。
本研究是针对LSI芯片中的繁杂交错的电源网络的电压降的精确分析进行的，并通过GPU并行处理技术实现算法的高速化。同时，为了适应GPU的高速化和节省内存（运行空间）的设计，提出了一套创新的数据结构（疎行列データ構造），最后实测结果比CPU处理快了17倍。
电子情报通信学会的英文论文集 IEICE Transactions on Electronics, IEICE Transactions on Information and Systems 中，被采用的论文为以下几篇：
本日（2013年03月26日）毕业典礼在京都市勧業館みやこめっせ举行，毕业证书递交仪式在電気総合館大講義室举办。按照本研究室惯例，在3号楼赤煉瓦玄関前进行了本研究室的毕业摄影。同学们，热烈祝贺你们光荣毕业！
本日（2013年03月25日）在京都市勧業館みやこめっせ举行了大学院学位授予典礼，按照本研究室惯例，在3号楼赤煉瓦玄関前进行了本研究室的毕业摄影。
（2010年《辞海》中，已经将“授与”基本都改写为“授于”）
平成25年3月12日（周二）18時30分开始，本研究室欢送会在京都ロイヤルホテル举行。
