Tag Archives: ISQED

ISQED 2017

Posted on Tuesday March 28th, 2017 by hiromoto

Mr. Morita presented his paper at International Symposium on Quality Electronic Design (ISQED) 2017 held in Santa Clara, CA. Mr. Morita’s talk was about the mitigation of the circuit degradation. Replacement of highly stressed logic gates with internal node control … Continue reading →

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(日本語) ISQED 2016

Posted on Wednesday March 23rd, 2016 by hiromoto

Sorry, this entry is only available in 日本語.

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ISQED2014

Posted on Sunday March 9th, 2014 by ts

Sorry, this entry is only available in 日本語.

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ISQED 2013

Posted on Thursday March 14th, 2013 by admin

Sorry, this entry is only available in 中文 and 日本語.

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ISQED2013 papers accepted

Posted on Tuesday November 27th, 2012 by admin

The following two papers are accepted for presentation at ISQED2013, which will be held at Santa Clara in March 2013. Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Multi-Trap RTN Parameter Extraction Based on Bayesian Inference,” International Symposium on Quality … Continue reading →

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ISQED2012 (03/19-03/21)

Posted on Tuesday May 1st, 2012 by admin

2012年3月19日〜21日に，アメリカ合衆国・カリフォルニア州Santa Clara，Techmart Centerにて開催された ISQED (The International Symposium on Quality Electronic Design) Symposium 2012 で，佐藤が研究成果の発表を行いました． Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, and Hiroyuki Ochi: “Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices,” in Proc. of International … Continue reading →

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参加学会2011年

Posted on Thursday March 29th, 2012 by admin

2011年03月14日～03月16日に，アメリカ合衆国・カリフォルニア州Santa Clara，Hyatt Regency HotelにてISQED(The International Symposium on Quality Electronic Design) Symposium 2011が開催され，M1(当時)の湯浅君が発表を行いました． Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs,” in Proc. of International Symposium on Quality Electrical … Continue reading →

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参加学会2010年

Posted on Thursday March 29th, 2012 by admin

2010年03月18日～03月19日に，アメリカ合衆国・カリフォルニア州San Francisco，Marriott Fisherman’s WharfにてTAU 2010(ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) )が開催され，B4(当時)の片山君が発表を行いました． Kentaro Katayama, Takanori Date, Hiroyuki Ochi, and Takashi Sato: “Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis,” … Continue reading →

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