Tag Archives: IEEE

(日本語) IEEEマイルストン贈呈式プレイベント

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(日本語) 第11回IEEE関西支部学生研究奨励賞 受賞

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Paper Published on IEEE Transactions on Device and Materials Reliability

The following article has been published on IEEE Transactions on Device and Materials Reliability. Hiromitsu Awano, Masayuki Hiromoto and Takashi Sato, “BTIarray: A Time-overlapping Transistor Array for Efficient Statistical Characterization of Bias Temperature Instability,” IEEE Transactions on Device and Materials … Continue reading

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(日本語) ICCAD2014 採択決定

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A paper has been accepted for publication in IEEE Transactions on Device and Materials Reliability

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A paper has been accepted for publication in IEEE Transactions on Device and Materials Reliability

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Our paper has been accepted for publication in IEEE Trans. on CAD

The following paper has been accepted for publication in IEICE Transactions on Electronics. Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, and Takashi Sato, “A Variability-Aware Adaptive Test Flow for Test Quality Improvement,” to appear in … Continue reading

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VMC2013

On Nov. 21, Mr. Awano presented his recent work on long term reliability of VLSI circuits at VMC2013 held in San Jose. Bias temperature instability (BTI) is considered to have significant impact on long term reliability of VLSI.  At the … Continue reading

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ASICON 2013

Prof. Sato gave a talk in ASICON 2013, which is held on Oct.28-31, 2013, in Shenzhen, China. Takashi Sato, “Statistical simulation methods for analyzing performance of low supply voltage circuits (invited),” in Proc. IEEE 10th International Conference on ASIC (ASICON), … Continue reading

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IEEE transaction paper (TED) has been published

A paper has been just published in the November issue of IEEE Transactions on Electron Devices. J.B. Velamala, K.B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, and Y. Cao, “Compact Modeling of Statistical BTI Under Trapping/Detrapping,”  IEEE Transactions … Continue reading

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