Tag Archives: IEEE

ACM/IEEE ASPDAC 2017

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Paper accepted for publication in IEEE Transactions on Very Large Scale Integration Systems

The following paper has been accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Hiromitsu Awano, Shumpei Morita, and Takashi Sato: “Scalable device array for statistical characterization of BTI-related parameters,” IEEE Transactions on Very Large Scale … Continue reading

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Student paper accepted for presentation in ISQED 2017

The following paper has been accepted for presentation in ISQED 2017 (International Symposium on Quality Electronic Design). Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “Comparative Study of Path Selection and Objective Function in Replacing NBTI Mitigation Logic,” … Continue reading

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Student paper accepted for presentation in ICMTS 2017

The following paper has been accepted for presentation in ICMTS 2017 (International Conference on Microelectronic Test Structures). Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “Input Capacitance Determination of Power MOSFETs from Switching Trajectories,” in Proc. of International Conference … Continue reading

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ATS 2016

Mr. Bian presented his paper at Asian Test Symposium (ATS 2016) held in International Conference Center Hiroshima, Japan. Song’s talk was on the mitigation of NBTI degradation in processors. Integrated circuits suffer from the so called aging effect, represented by … Continue reading

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(日本語) VMC 2016

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WiPDA 2016

Dr. Shintani and Mr. Oishi presented their papers at the IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA) held in Fayetteville, AR, USA. Dr. Shintani’s presentation was about a circuit simulation model for V-groove SiC power MOSFET with … Continue reading

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Papers accepted for presentation in VMC 2016

The following papers have been accepted for presentation in VMC2016 (IEEE/ACM Workshop on Variability Modeling and Characterization). Michihiro Shintani, Kazuki Oishi, Rui Zhou, Masayuki Hiromoto, and Takashi Sato: “Unique Device Identification Framework for Power MOSFETs Using Inherent Device Variation,” in Proc. … Continue reading

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Paper accepted for presentation in APEC 2017

The following paper has been accepted for presentation in APEC2017 (the 32nd Annual IEEE Applied Power Electronics Conference & Exposition). Michihiro Shintani, Kazuki Oishi, Rui Zhou, Masayuki Hiromoto, and Takashi Sato: “Device Identification from Mixture of Measurable Characteristics,” in Proc. … Continue reading

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(日本語) SISPAD2016

Dr. Shintani presented his paper at the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) held in Nuremberg, Germany. SISPAD has provided an international forum for the presentation of leading-edge research and development results in the area of … Continue reading

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