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May 2025 M T W T F S S « Apr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Archives
ACM/IEEE ASPDAC 2013
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Journal papers published on Trans. IEICE
The following papers are published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Special Section on “VLSI Design and CAD Algorithms”.
- Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Bayesian Estimation of Multi-Trap RTN Parameters using Markov Chain Monte Carlo Method,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E95-A, No.12, pp.2272-2283, Dec., 2012. (Kyoto University repository)
- Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E95-A, No.12, pp.2242-2250, Dec., 2012. (Kyoto University repository)
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2012 ICD Conference
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2012 IEEE Student Branch Leadership Training Workshop in Japan Council at Meiji University
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Year-end party
Year-end party will be held on 25th December from 7 p.m. at Kyoto Kiyamachi.
Prof. Yukihiro Nakamura as well as current members of our laboratory will attend the party. If you are an alumnus and can attend the party, please contact us for the details.
Accepted for publication in IEICE Transactions on Electronics, Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology
The following two papers has been accepted for publication in IEICE Transactions on Electronics, Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology.
- Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Parallel Acceleration Scheme for Monte Carlo Based SSTA using Generalized STA Processing Element,” IEICE Transactions on Electronics, Apr. 2013 (to appear).
- Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis,” IEICE Transactions on Electronics, Apr. 2013 (to appear).
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APSIPA ASC 2012
On 5th 2012, Assistant Professor Tsutsui presented the following work at Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC) 2012, which was held in Hollywood, LA from 3rd to 6th, 2012.
- Hiroshi Tsutsui, Satoshi Yoshikawa, Hiroyuki Okuhata, and Takao Onoye, “Halo Artifacts Reduction Method for Variational Based Realtime Retinex Image Enhancement,” in Proc. of APSIPA ASC 2012, Dec. 2012.
JST International Symposium on Dependable VLSI Systems 2012
We have gave a poster presentation at JST International Symposium on Dependable VLSI Systems 2012 which was held on 1st 2012 at Fujisoft Akiba Plaza 5F Akiba Hall. The theme of this research is “dependable VLSI platform using robust fabrics“, whose principal investigator is Prof. Onodera (Kyoto University). This research is supported by JST CREST.
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Design Gaia 2012
Zhi Li (master course 2nd degree) has made a presentation about his work at Design Gaia 2012.
- Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Accurate I/O Buffer Impedance Self-Adjustment using Vth and Temperature Sensors,” IEICE Technical Report, Vol.112, No.320, VLD2012-79, DC2012-45, pp.117-122, Nov. 2012.