The following paper has been accepted for publication in IEICE Transactions on Electronics.
Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, and Takashi Sato, “A Variability-Aware Adaptive Test Flow for Test Quality Improvement,” to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
The following paper has been accepted for publication in IEICE Transactions on Electronics.
The following paper has been published on the January issue of Trans. IEICE(Kyoto University repository).
This was a joint work with Murata Manufacturing, Co. Ltd., Tokyo Institute of Technology, and our group in Kyoto University.
End-of-year party has been held on December 18th, 2013. We had a great SUKIYAKI dinner looking back this past year and looking forward to a new year.
On Dec. 9, professor Rung-Bin Lin and his students came to Kyoto University. Our laboratory hosted their visit and hold an exchange meeting, including introductions, discussions, a campus tour and lunch. It was very good experience for the students to interact with the oversea students.
On Dec. 9, professor Rung-Bin Lin and his students came to Kyoto University. Our laboratory hosted their visit and hold an exchange meeting, including introductions, discussions, a campus tour and lunch. It was very good experience for the students to interact with the oversea students.
End-of-year party will be held at 7pm on December 18th, 2013. For alumni and alumnae: please RSVP to the faculties by December 17th.
After the VMC2013 workshop, Sato visited the d.school at Stanford University.
After the VMC2013 workshop, Sato visited the d.school at Stanford University.
On Nov. 21, Mr. Awano presented his recent work on long term reliability of VLSI circuits at VMC2013 held in San Jose.
Bias temperature instability (BTI) is considered to have significant impact on long term reliability of VLSI. At the workshop, he presented variability of BTI degradation measured on hundreds of transistors. Measuring BTI degradation has taken days or even weeks even in accelerated conditions. Hence, measurements of BTI on many transistors and analyzing its variability has been almost impossible.
He successfully shorted the measurement time by devising a circuit that overlaps the stress/recovery time over many transistors. By taking its variability into account, optimistic or pessimistic prediction of degradation can be prevented.
Prof. Sato gave a talk in ASICON 2013, which is held on Oct.28-31, 2013, in Shenzhen, China.
Takashi Sato, “Statistical simulation methods for analyzing performance of low supply voltage circuits (invited),” in Proc. IEEE 10th International Conference on ASIC (ASICON), pp.103-106, September, 2013. (Best Western Shenzhen Felicity Hotel, Shenzhen, China)
This paper reviews statistical simulation methods that can efficiently and accurately handle device parameter variability. Technical discussions with Chinese professors were very fruitful. A visit to Shenzhen’s famous electronic markets around Huaqiangbei Road was really stimulating.
A paper has been just published in the November issue of IEEE Transactions on Electron Devices.
J.B. Velamala, K.B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, and Y. Cao, “Compact Modeling of Statistical BTI Under Trapping/Detrapping,” IEEE Transactions on Electron Devices, vol.60, no.11, pp.3645-3654, Nov. 2013. (doi: 10.1109/TED.2013.2281986)
URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6612719&isnumber=6637023
This paper proposes a new device model for aging simulations for circuits. A statistical compact model for BTI (Bias temperature instability) is presented, and it is validated with 65-nm silicon data. Using the proposed model, reliability design of electronic systems will be enhanced, promoting to realize a safe society.
This work was jointly conducted with Arizona State University and Universidade Federal do Rio Grande do Sul.
