Hiromitsu Awano (D2) gave a presentation at DA Symposium 2014 (in Gero, Gifu) on the long-term reliability of VLSI circuits. The symposium was hold on August 28~29th, 2014, and the presentation was given on 28th August, 2014.
As process technology pushes semiconductors to be even smaller, failures resulted from material degradation have became more and more problematic. In particular, Negative Bias Temperature Instability (NBTI) is becoming one of the major concerns as this degradation mechanism will dramatically slow the switching speed of transistors. However, modern nano-scale transistors tend to be greatly varied in their physical characteristics. Hence, to understand NBTI, measurements have to be taken statistically on a group of transistors that possess characteristic variation. As a result, a large amount of measurement data have to be taken in order to model the characteristic variation of transistors. Hence, we have been focusing on designing circuitry and test chips that can measure these variations efficiently. Awano’s presentation had shown that several thousands of transistors can be measured at once, a lot more than the conventionally-known number at around one hundred. The result of the experiment measuring varied degradation characteristics of 4k transistors was discussed in the presentation. It was determined that the variation in degradation of a transistor is inversely proportional to its channel area. This conclusion suggested that degradation variation increases rapidly as the scale of transistors further shrinks.
The following article is only available in Japanese:
- 粟野 皓光, 廣本 正之, 佐藤 高史:
“3996トランジスタにおけるNBTI劣化の統計的ばらつき”, 情報処理学会DAシンポジウム2014 (於 岐阜県下呂市 ホテル下呂温泉水明館), pp.3-8, 2014年8月.
