Processor Architecture and Systems Synthesis Laboratory

The following paper has been accepted for presentation in ISQED 2016.

• Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, and Takashi Sato:
  “Nonlinear Delay-Table Approach for Full-Chip NBTI Degradation Prediction,” in Proc. of International Symposium on Quality Electronic Design (ISQED) (Santa Clara, CA), Mar. 2016 (to appear).

The following papers are accepted for publication in TAU workshop 2016, congratulations!

• Hiromitsu Awano and Takashi Sato:
  “Efficient Transistor-Level Timing Yield Estimation via Line Sampling,” in Proc. of ACM/IEEE International Workshop on Timing Issues (TAU) (Santa Rosa, CA), Mar. 2016 (to appear).
• Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, and Takashi Sato:
  “Mitigation of NBTI-Induced Timing Degradation in Processor,” in Proc. of ACM/IEEE International Workshop on Timing Issues (TAU) (Santa Rosa, CA), Mar. 2016 (to appear).

The paper below has been accepted for ISCAS2016, which will be held in May 2016 at Montreal, Canada.

• Motoki Yoshinaga, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato:
  “Physically Unclonable Function using RTN-Induced Delay Fluctuation in Ring Oscillators,” IEEE International Symposium on Circuits and Systems (ISCAS) (Montreal, Canada), May 2016 (to appear).