Baseball tournament 2016

Posted on Wednesday August 10th, 2016 by hiromoto

The first round of EE baseball tournament was held on Aug. 9th at the Kyoto Imperial Palace ground. We played well, but only to lose the game.

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SASIMI 2016: three student papers accepted

Posted on Friday August 5th, 2016 by hiromoto

The following papers has been accepted for presentation in the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016). The workshop will be held in October 24 and 25, 2016 in Kyoto.

  • Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Thermal Circuit Identification of Power MOSFETs through In-Situ Channel Temperature Measurement,” in Proc. of the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016) (Kyoto Research Park, Kyoto, Japan), Oct. 2016 (to appear).
  • Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Path Grouping Approach for Efficient Candidate Selection of Replacing NBTI Mitigation Logic,” in Proc. of the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016) (Kyoto Research Park, Kyoto, Japan), Oct. 2016 (to appear).
  • Takayuki Ujiie, Masayuki Hiromoto, and Takashi Sato:
    “Hardware Accelerator of Convolutional Neural Network for Image Recognition and its Performance Evaluation Platform,” in Proc. of the 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2016) (Kyoto Research Park, Kyoto, Japan), Oct. 2016 (to appear).
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SSDM 2016: paper accepted

Posted on Tuesday July 19th, 2016 by hiromoto

The following paper has been accepted for presentation in International Conference on Solid State Devices and Materials (SSDM), which will be held during September 26-29, 2016.

  • Michihiro Shintani, Yohei Nakamura, Masayuki Hiromoto, Takashi Hikihara, and Takashi Sato:
    “A Surface-Potential-Based Reverse-Transfer Capacitance Model for Vertical SiC DMOSFET,” in Proc. of International Conference on Solid State Devices and Materials (SSDM) (Tsukuba, Japan), Sep. 2016 (to appear).
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IPSJ Computer Science Research Award for Young Scientists

Posted on Saturday July 16th, 2016 by hiromoto

Dr. Awano, an alumnus of our group, and S. Bian, a master course student, will receive the “IPSJ Computer Science Research Award for Young Scientists” on the following papers. The award ceremony will be held on September 14th, 2016, during DA symposium.

  • 粟野 皓光, 廣本 正之, 佐藤 高史:
    “デバイス特性の経年劣化に起因する不良確率変化の効率的な解析手法”, 情報処理学会DAシンポジウム2015 (於 石川県加賀市山代温泉 ゆのくに天祥), pp.169-174, 2015年8月.
  • Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Fast Estimation on NBTI-Induced Delay Degradation Based on Signal Probability,” 情報処理学会DAシンポジウム2015 (於 石川県加賀市山代温泉 ゆのくに天祥), pp.181-186, Aug. 2015.
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(日本語) 電気学会 半導体電力変換研究会

Posted on Saturday July 16th, 2016 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) CVPRW/EVW2016

Posted on Tuesday July 5th, 2016 by hiromoto

Sorry, this entry is only available in 日本語.

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NOLTA2016: papers accepted

Posted on Monday July 4th, 2016 by hiromoto

The following papers have been accepted for presentation in International Symposium on Nonlinear Theory and Its Applications (NOLTA). The symposium will be held in November 27-30, 2016 in Yugawara, Japan.

  • Rui Zhou, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “A Charge-Based SiC Power MOSFET Model Considering On-State Resistance,” in Proc. of International Symposium on Nonlinear Theory and Its Applications (NOLTA) (Yugawara, Japan), Nov. 2016 (to appear).
  • Michihiro Shintani, Yuchong Sun, Hiroo Sekiya, and Takashi Sato:
    “A Design Example of Class-E Based Gate Driver for High Frequency Operation of SiC Power MOSFET,” in Proc. of International Symposium on Nonlinear Theory and Its Applications (NOLTA) (Yugawara, Japan), Nov. 2016 (to appear).
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Article on our DAC2016 paper

Posted on Thursday June 23rd, 2016 by ts

Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.

2016-06-23_100327

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A paper presented at DAC2016

Posted on Wednesday June 15th, 2016 by ts

Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx.

His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations considering a large number of variables have been successfully conducted in a practical time. Experimental results indicated the analysis containing more than 1000 variable becomes possible and approximately 300x acceleration has been achieved. The proposed method is particularly useful to analyze highly parallelized processors, such as GPU, designed using an advanced technology node.

DAC is the largest and most prestigious conference in this area (acceptance ratio: 22.6% = 152/674).
A large number of attendees gather to the conference which is held in conjunction with a huge exhibition and collocated workshops.

  • Hiromitsu Awano and Takashi Sato, “Efficient transistor-level timing yield estimation via line sampling,” in Proc. Design automation conference (DAC), paper 69.3, June 2016.
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SISPAD2016: paper accepted

Posted on Monday June 13th, 2016 by hiromoto

The paper below has been accepted for presentation in International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). This is a joint work with laboratory of Advanced Electrical Systems Theory, Department of Electrical Engineering at Kyoto University.

  • Yohei Nakamura, Michihiro Shintani, Kazuki Oishi, Takashi Sato, and Takashi Hikihara:
    “A Simulation Model for SiC Power MOSFET Based on Surface Potentiantial,” in Proc. of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (Nuremberg, Germany), Sep. 2016 (to appear).
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