(日本語) 情報処理学会コンピュータサイエンス領域奨励賞 受賞

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(日本語) SLDM研究会 最優秀発表学生賞 受賞

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(日本語) DAシンポジウム2015優秀発表学生賞 受賞

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(日本語) DAシンポジウム2016

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(日本語) SISPAD2016

Dr. Shintani presented his paper at the International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) held in Nuremberg, Germany.

SISPAD has provided an international forum for the presentation of leading-edge research and development results in the area of process and device simulation for 20 years. Recently, works related wide bandgap power devices, such as SiC, have been included in SISPAD. Dr. Shintani’s talk was about a SiC power MOSFET model for circuit simulations. The proposed model is based on physical behavior of the SiC MOSFET and thus can successfully predict the circuit performance that utilizes SiC power MOSFET. With fruitful discussion with prominent researchers during the conference, it was an excellent opportunity to exchange ideas for future research plans.

This work is a collaborative research with Takashi Hikihara Laboratory, Department of Electrical Engineering, Kyoto University.

  • Yohei Nakamura, Michihiro Shintani, Kazuki Oishi, Takashi Sato, and Takashi Hikihara:
    “A Simulation Model for SiC Power MOSFET Based on Surface Potentiantial,” in Proc. of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (Nuremberg, Germany), pp.121-124, Sep. 2016.
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Papers accepted for presentation in WiPDA 2016

The following papers have been accepted for presentation in WiPDA (the 4th IEEE Workshop on Wide Bandgap Power Devices and Applications).

  • Michihiro Shintani, Kazuki Oishi, Rui Zhou, Masayuki Hiromoto, and Takashi Sato:
    “A Circuit Simulation Model for V-Groove SiC Power MOSFET,” in Proc. of the 4th IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA) (Fayetteville, AR, USA), Nov. 2016 (to appear).
  • Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Identifications of Thermal Equivalent Circuit for Power MOSFETs through In-Situ Channel Temperature Estimation,” in Proc. of the 4th IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA) (Fayetteville, AR, USA), Nov. 2016 (to appear).
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Paper accepted for presentation in ASP-DAC 2017

The following paper has been accepted for presentation in ASP-DAC 2017 (Asia and South Pacific Design Automation Conference). Acceptance rate 31%=111/358.

  • Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato:
    “Efficient Circuit Failure Probability Calculation Along Product Lifetime Considering Device Aging,” 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017) (Chiba/Tokyo, Japan), Jan. 2017 (to appear).
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Paper accepted for publication in Journal of Electronic Testing: Theory and Applications

Following paper has been accepted for publication in Journal of Electronic Testing: Theory and Applications (JETTA).

  • Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, and Takashi Sato:
    “Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing,” Journal of Electronic Testing: Theory and Applications, Oct. 2016 (to appear).
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Lab Trip 2016

The lab took a trip to Ise and Toba on August 18th and 19th. We first visited Ise Jingu (a.k.a., Ise Grand Shrine) and toured around Sengu-kan, studied the history of and stories behind Shikinen-Sengu (A tradition of Japanese shrine where sacred buildings in the shrine are re-positioned and completely reconstructed from ground up. This reposition process, named as Shikinen-Sengu, generally happens once per 20 or more years).
Then in Toba, we went to the Dolphin Island and cruised around the Toba bay. The crowd then enjoyed sightseeing in Toba aquarium, host for a great variety of interesting sea creatures.

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Lab tour 2016

Kyoto University open campus was held on Aug. 9 and 10. As a part of the open campus, we hosted lab tours for high school students.

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