The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP).
The following paper has been accepted for presentation in ISQED 2017 (International Symposium on Quality Electronic Design).
The following paper has been accepted for presentation in ICMTS 2017 (International Conference on Microelectronic Test Structures).
Dr. Shintani and Mr. Zhou presented their papers at International Symposium on Nonlinear Theory and Its Applications (NOLTA 2016) held in Yugawara, Japan.
Dr. Shintani’s talk was on the gate driver without its switching loss. As switching frequency increases, the size of power converters can be reduced. On the other hand, switching loss of the gate driver becomes a big issue. In this work, we proposed a gate driver using soft-switching technique based on class-E amplifier. We demonstrated the proposed gate driver achieve no switching loss and target power MOSFET is successfully switched. This work is a collaborative work with Hiroo Sekiya Laboratory, Chiba University.
Mr. Zhou’s talk was about a circuit simulation model for SiC power MOSFET. Accurate transistor model is the key component in designing efficient power converters. Its importance is increasing as the operating frequency of the converters become higher. A transistor model that accurately and compactly represents physical device behavior is required. In this paper, we propose a charge-based transistor model that includes parasitic resistances of vertical diffused SiC power MOSFET. Through experiments using a commercial device, good agreement has been observed between measurement and simulation in I-V, C-V, and transient characteristics.
Mr. Bian presented his paper at Asian Test Symposium (ATS 2016) held in International Conference Center Hiroshima, Japan.
Song’s talk was on the mitigation of NBTI degradation in processors. Integrated circuits suffer from the so called aging effect, represented by the negative bias temperature instability (NBTI) phenomenon, where the circuit delay gradually (and significantly) degrades over years. This work tries to address the worst-case delay degradation by employing special logic gate, known as the internal control (INC) logic, controlled by the NOP instruction to mitigate NBTI-induced aging degradation in processors. In addition, to minimize the number of INC logic, genetic optimization is used to find the quasi-optimal solution to the problem. Through numerical experiment, it is demonstrated that
delay degradation is mitigated by as much as 45%, translating to a lifespan extension of around 6 times.
Sorry, this entry is only available in 日本語.
Sorry, this entry is only available in 日本語.
Dr. Shintani and Mr. Oishi presented their papers at the IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA) held in Fayetteville, AR, USA.
Dr. Shintani’s presentation was about a circuit simulation model for V-groove SiC power MOSFET with buried P-layers. By burying the P-layers, the reliability of the V-groove SiC power MOSFET is dramatically improved. In this work, a circuit simulation model for V-groove SiC power MOSFET with buried P-layers is proposed. From results of the process simulations, the voltage dependency of the capacitance characteristics is accurately modeled. Through experiments using a V-groove SiC MOSFET with buried P-layers, it is demonstrated that the proposed model successfully reproduces static characteristics.
Mr. Oishi’s presentation was about measurement of thermal circuit of power MOSFETs. We have proposed two measurement techniques. In the presentation, the two methods are validated by the comparison between each of the methods’ result. Furthermore, the advantages and disadvantages of each technique are discussed.
Sorry, this entry is only available in 日本語.
The following paper has been accepted for presentation in DATE 2017 (Design, Automation & Test in Europe). The acceptance rate for regular papers is 24%.
