Student paper accepted for publication in IEICE journal

Posted on Tuesday February 28th, 2017 by hiromoto

Following paper written by M1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

  • Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, July 2017 (to appear).
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(日本語) 第13回IEEE関西支部学生研究奨励賞 受賞

Posted on Sunday February 26th, 2017 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) IEEE PELS Japan Young Engineer Award 受賞

Posted on Monday February 20th, 2017 by hiromoto

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Lab tour for EE students

Posted on Monday February 20th, 2017 by hiromoto

Lab tour for prospective senior students in EE has been held on
Feb. 20, 2017.  Students who are interested in joining our group but
missed the lab tour, contact us via e-mail.

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Student paper accepted for presentation in DAC 2017

Posted on Monday February 13th, 2017 by hiromoto

The following paper has been accepted for presentation in DAC 2017
(ACM/IEEE Design Automation Conference).

  • Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations,” in Proc. of ACM/IEEE Design Automation Conference (DAC) (Austin, TX), June 2017 (to appear).
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(日本語) 3回生（研究室配属対象者）の皆さんへ

Posted on Sunday February 5th, 2017 by hiromoto

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ACM/IEEE ASPDAC 2017

Posted on Wednesday January 25th, 2017 by ts

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Paper accepted for publication in IEEE Transactions on Very Large Scale Integration Systems

Posted on Thursday January 5th, 2017 by ts

The following paper has been accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (TVLSI).

  • Hiromitsu Awano, Shumpei Morita, and Takashi Sato:
    “Scalable device array for statistical characterization of BTI-related parameters,”
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
    DOI: 10.1109/TVLSI.2016.2638021
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(日本語) 第42回パルテノン研究会

Posted on Tuesday December 20th, 2016 by hiromoto

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(日本語) 2016年度 忘年会

Posted on Monday December 19th, 2016 by hiromoto

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