DATE 2017

Mr. Song Bian presented his paper at Design, Automation and Test  in Europe (DATE) 2017 held in Lausanne, Switzerland. The acceptance rate of oral presentation is 24%.

Song’s talk was on the realization of a secured content addressable memory (CAM) based on homomorphic encryption. Recent years, information leakage through search and access pattern is a serious issue in data outsourcing. In this work, we proposed a SCAM construct that retains the high parallel performance of SCAM while hiding access pattern. We used
an additive homomorphic encryption scheme to implement the word matching function, and achieved a 400x speed improvement on CPU and 40,000x power reduction on specialized hardware, when compared to existing work.

  • Song Bian, Masayuki Hiromoto, and Takashi Sato:
    “SCAM: Secured Content Addressable Memory Based on Homomorphic Encryption,” in Proc. of Design, Automation & Test in Europe (DATE), pp.984-989, Mar. 2017.
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APEC 2017

Dr. Shintani presented his paper at IEEE Applied Power Electronics Conference and Exposition (APEC) 2017 held in Tampa, FL, USA.

Dr. Shintani’s presentation was a pioneer work on the security of power devices. APEC is the leading conference in the field of power electronics. During the conference, more than 3,000 researchers and developers attended and thoroughly discussed. Moreover, more than 100 power electronics companies exhibited in the exposition that was held in conjunction with APEC. We were highly inspired by the contact with the technologies and product of the state-of-art power electronics.

  • Michihiro Shintani, Kazuki Oishi, Rui Zhou, Masayuki Hiromoto, and Takashi Sato:
    “Device Identification from Mixture of Measurable Characteristics,” in Proc. of the 32nd Annual IEEE Applied Power Electronics Conference & Exposition (APEC), Mar. 2017.
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ICMTS 2017

Mr. Oishi presented his paper at International Conference on Microelectronic Test Structures (ICMTS) 2017 held in Grenoble, France.

Mr. Oishi’s talk was about input capacitance measurement of power MOSFETs. The modeling of the input capacitance is crucial for the simulation of power converters. However, conventional methods could not measure the capacitance accurately when the channel of MOSFET is formed. In this paper, we propose a novel method for determining the input capacitance using switching waveforms. The proposed method enables the capacitance measurement even when the channel is formed. The experimental results show that the capacitance model obtained by the proposed method simulates switching waveforms accurately and reduces timing errors by more than 16 times when compared to the conventional model.

  • Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Input Capacitance Determination of Power MOSFETs from Switching Trajectories,” in Proc. of International Conference on Microelectronic Test Structures (ICMTS), pp.87-92, Mar. 2017.
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(日本語) 2017年 電子情報通信学会 総合大会

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Graduation Ceremony

Graduation Ceremony was held at Miyako-Messe (Kyoto International
Exhibition Hall). hat toss!

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Degree conferment ceremony

Degree conferment ceremony for masters has been held at Miyako-Messe (Kyoto
International Exhibition Hall).

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Farewell party 2017

Pictures at the farewell party.

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ISQED 2017

Mr. Morita presented his paper at International Symposium on Quality Electronic Design (ISQED) 2017 held in Santa Clara, CA.

Mr. Morita’s talk was about the mitigation of the circuit degradation. Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. Various INC replacement algorithms have been proposed, but there are no evaluations for the necessity of the signal probability update and the aged delay calculation during optimization, which are highly CPU intensive. Also, the mitigation effectiveness and optimization time have not been fully evaluated. In this paper, strategies for selecting replacement candidates and the objective functions in optimization are evaluated using an example processor design.  From the experimental result, it is found that the recalculation of the signal probability and the aged path delay greatly improves the optimization results. It is also found that the evaluated path limitation through path clustering with the average objective function reduces calculation time, without degrading the mitigation gain.

  • Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “Comparative Study of Path Selection and Objective Function in Replacing NBTI Mitigation Logic,” in Proc. of International Symposium on Quality Electronic Design (ISQED) (Santa Clara, CA), pp.426-431, Mar. 2017.
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(日本語) 第30回 回路とシステムワークショップ 採択決定

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(日本語) 2017年3月SIS研究会

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