Processor Architecture and Systems Synthesis Laboratory

Mr. Song Bian presented his paper in Design Automation Conference (DAC) 2017 held in Austin, Tx.

Song’s presentation was on creating learning-based STA libraries for characterizing aging-induced device variations. Traditional approach to the accurate characterization of aging (specifically negative bias temperature instability (NBTI) studied in this work) is to build an interpolation-based high-dimensional library which is prohibitive in library creation time. In this work, we proposed a regression-based learning approach to the making of STA library. In our approach, a learning algorithm will be optimized to learn the  relationship between aging-induced variations and aged delay, where the aged delays are given as correct training data. The optimized algorithm will then be used as the STA library to predict the delay of gates in test designs. Through experiment, we achieved an maximum absolute error of less than 4%, demonstrating that accurate STA can be carried out without the need of high-dimensional interpolation.

DAC is the largest and most prestigious conference in this area. A large number of attendees gather to the conference which is held in conjunction with a huge exhibition and collocated workshops.

• Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
  “LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations,” in Proc. of ACM/IEEE Design Automation Conference (DAC), 73.3, June 2017.
  DOI: 10.1145/3061639.3062280