Tag Archives: IEICE

The following paper has been accepted for publication in Nonlinear Theory and Its Applications, IEICE. Rui Zhou, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “Modeling of Interelectrode Parasitic Elements of V-Groove SiC MOSFET,” Nonlinear Theory and Its Applications, IEICE, (to appear).

The following paper has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Satoshi Yamamori, Masayuki Hiromoto, and Takashi Sato: “Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update,” IEICE … Continue reading →

The following paper has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Masayuki Hiromoto, Motoki Yoshinaga, and Takashi Sato: “MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output … Continue reading →

The following paper has been published on IEICE Transactions on Information and Systems. An area-efficient FPGA-based annealing processor that is based on Ising model is proposed. The proposed processor eliminates random number generators (RNGs) and temperature schedulers, which are the … Continue reading →

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms … Continue reading →

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. A circuit-aging simulation that efficiently calculates temporal change of rare circuit-failure probability is proposed. While conventional methods required a long computational time due … Continue reading →