Processor Architecture and Systems Synthesis Laboratory

Following paper written by D1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

• Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato:
  “Identification and Application of Invariant Critical Paths under NBTI Degradation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2017 (to appear).

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.

• Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
  “Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.7, pp.1464-1472, July 2017.
  DOI: 10.1587/transfun.E100.A.1464