Processor Architecture and Systems Synthesis Laboratory

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

A circuit-aging simulation that efficiently calculates temporal change of rare circuit-failure probability is proposed. While conventional methods required a long computational time due to the necessity of conducting separate calculations of failure probability at each device age, the proposed Monte Carlo based method requires to run only a single set of simulation. By applying the augmented reliability and subset simulation framework, the change of failure probability along the lifetime of the device can be evaluated through the analysis of the Monte Carlo samples. Combined with the two-step sample generation technique, the proposed method reduces the computational time to about 1/6 of that of the conventional method while maintaining a sufficient estimation accuracy.

• Hiromitsu Awano and Takashi Sato:
  “Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, pp.2807-2815, Dec. 2017.
  DOI: 10.1587/transfun.E100.A.2807

Following paper written by M2 student has been accepted for publication in IEICE Transactions on Information and Systems.

• Hidenori Gyoten, Masayuki Hiromoto, and Takashi Sato:
  “Area Efficient Annealing Processor for Ising Model without Random Number Generator,” IEICE Transactions on Information and Systems, Vol.E101-D, No.2, Feb. 2018 (to appear).
  DOI: 10.1587/transinf.2017RCP0015