The following paper has been accepted for presentation in the IEEE International Symposium on Circuits and Systems (ISCAS) 2018. The conference will be held in May 27-30, 2018 in Florence, Italy.
Sorry, this entry is only available in 日本語.
The following paper has been accepted for presentation in International Power Electronics Conference (IPEC2018). The conference will be held in May 20-24, 2018 in Niigata, Japan.
Sorry, this entry is only available in 日本語.
The following papers have been accepted for presentation in the 21st Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2018). The workshop will be held in March 26 and 27, 2018 in Shimane.
The following paper has been published on IEEE Transactions on Biomedical Engineering.
The photoplethysmographic (PPG) signal is an important source of information for estimating heart rate (HR). However, the PPG signal could be strongly contaminated by the motion artifact of the subjects, making HR estimation a particularly difficult problem. In this paper, we propose PARHELIA, a PARticle filter-based algorithm for HEart rate estimation using photopLethysmographIc signAls. The proposed method employs a particle filter, and utilizes the simultaneously recorded acceleration signals from a wrist-type sensor, to keep track of multiple HR candidates. This achieves quick recovery from incorrect HR estimations under the strong influence of the MA. Experimental results for a dataset of 12 subjects recorded during fast running showed that the average absolute estimation error was 1.17 beats per minute (BPM) whereas that of the best-known conventional method, JOSS, is 1.28 BPM. Furthermore, the estimation time of PARHELIA is 20 times shorter than JOSS.
Sorry, this entry is only available in 日本語.
Sorry, this entry is only available in 日本語.
The following paper has been accepted for presentation in ISQED 2018 (International Symposium on Quality Electronic Design).
The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.
