The following paper has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
The following paper has been accepted for presentation in the IEEE International Memory Workshop (IMW) 2018. The conference will be held in May 14-16, 2018 in Kyoto.
Sorry, this entry is only available in 日本語.
Sorry, this entry is only available in 日本語.
The following paper has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
Sorry, this entry is only available in 日本語.
The following paper has been published on IEICE Transactions on Information and Systems.
An area-efficient FPGA-based annealing processor that is based on Ising model is proposed. The proposed processor eliminates random number generators (RNGs) and temperature schedulers, which are the key components in the conventional annealing processors and occupying a large portion of the design. Instead, a shift-register-based spin flipping scheme successfully helps the Ising model from stucking in the local optimum solutions. An FPGA implementation and software-based evaluation on max-cut problems of 2D-grid torus structure demonstrate that our annealing processor solves the problems 10-10000 times faster than conventional optimization algorithms to obtain the solution of equal accuracy.
Sorry, this entry is only available in 日本語.
The following paper has been accepted for publication in IEEE Transactions on Power Electronics (TPEL).
Mr. Shumpei Morita presented his paper in the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC 2018) held in Jeju Island, Korea.
Morita’s talk was about the analysis of the circuit degradation. The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads, and thus path delay degradation is strongly dependent on each use case. In this paper, we propose a subset simulation (SS) framework that efficiently and accurately finds the worst case workload and the failure probability covering various workloads. In the proposed method, workloads that yield worst aged delay are efficiently generated by the NBTI-aware Markov chain Monte Carlo method. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to the naive Monte Carlo method. From the result of the SS, feasible workload that gives worst aged delay is obtained.
