Tag Archives: IEEE

The 72nd IEEE Kansai Section Lecture Meeting | Mr. Deepak Mathur (IEEE Region 10 Humanitarian Technology Coordinator)

Posted on Thursday August 2nd, 2012 by admin

A lecture about Humanitarian Technology by Mr. Deepak Mathur (IEEE Region 10 Humanitarian Technology Coordinator) was held at Building 3, Faculty of Engineering, Kyoto University on August 2.  Mr. Kawashima (master course student) has partially arranged this lecture as chair of IEEE Student Branch … Continue reading →

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IEEE VTS’12 (04/23-26)

Posted on Wednesday June 13th, 2012 by admin

2012年4月23日〜26日に，アメリカ合衆国・ハワイ州，Hyatt Mauiにて IEEE VTS’12 (30th VLSI Test Symposium) が開催され，D2 新谷が発表を行いました． Michihiro Shintani and Takashi Sato, “A Bayesian-based process parameter estimation using IDDQ current signature,” IEEE VLSI test symposium (VTS), pp.86-91, April, 2012.

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ISQED2012 (03/19-03/21)

Posted on Tuesday May 1st, 2012 by admin

2012年3月19日〜21日に，アメリカ合衆国・カリフォルニア州Santa Clara，Techmart Centerにて開催された ISQED (The International Symposium on Quality Electronic Design) Symposium 2012 で，佐藤が研究成果の発表を行いました． Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, and Hiroyuki Ochi: “Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices,” in Proc. of International … Continue reading →

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TAU’12 (01/18-01/20)

Posted on Thursday March 29th, 2012 by admin

2012年1月18日〜20日に，台湾・台北市，National Taiwan Universityにて TAU ’12 Workshop (The 19th ACM/IEEE International Workshop o Timing Issues in the Specification and Synthesis of Digital Systems) が開催され，M2 湯浅が発表を行いました． Hiroshi Yuasa, et.al., “Acceleration Scheme for Monte Carlo based SSTA using Generalized STA Processing Element”

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参加学会2011年

Posted on Thursday March 29th, 2012 by admin

2011年03月14日～03月16日に，アメリカ合衆国・カリフォルニア州Santa Clara，Hyatt Regency HotelにてISQED(The International Symposium on Quality Electronic Design) Symposium 2011が開催され，M1(当時)の湯浅君が発表を行いました． Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs,” in Proc. of International Symposium on Quality Electrical … Continue reading →

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参加学会2010年

Posted on Thursday March 29th, 2012 by admin

2010年03月18日～03月19日に，アメリカ合衆国・カリフォルニア州San Francisco，Marriott Fisherman’s WharfにてTAU 2010(ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) )が開催され，B4(当時)の片山君が発表を行いました． Kentaro Katayama, Takanori Date, Hiroyuki Ochi, and Takashi Sato: “Sequential Importance Sampling for Low-Probability and High-Dimensional SRAM Yield Analysis,” … Continue reading →

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