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May 2025 M T W T F S S « Apr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Archives
Category Archives: Conference/Workshop
VMC2012
On November 8th, Prof. Sato presented the following work (poster presentation) at VMC2012 (IEEE/ACM Workshop on Variability Modeling and Characterization 2012), which was held in San Jose, CA. Michihiro Shintani and Takashi Sato, “Adaptive Current-Threshold Determination for Accurate IDDQ Testing,” … Continue reading
EPEPS2012 (2012/10/22-24)
We presented the following work at EPEPS2012 (21st Conference on Electrical Performance of Electronic Packaging and Systems), which was held in Tempe Mission Palms Hotel, Tempe, AZ, from Oct. 22 to 24. This work is a collaborative research with Murata … Continue reading
DA Symposium 2012
Mr. Shimizu presented his work at the IPSJ DA Symposium 2012 held at Hotel Gero onsen Suimeikan, August 29 to 30. Hirofumi Shimizu, Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato, “Estimation of Model Parameters for Random Telegraph Noise Based … Continue reading
The 25th Workshop on Circuits and Systems @Awaji Yumebutai International Conference Center
On July 30th, Mr. Morishita and Mr. Kawashima, who are master course students, have presented their works at the 25th Workshop on Circuits and Systems held at Awaji Yumebutai International Conference Center. Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi … Continue reading
Posted in Conference/Workshop
Tagged IEICE, KWS
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スマートインフォメディアシステム(SIS)研究会(6/14-15)@帯広市とかちプラザ
2012年6月14日〜15日に帯広市とかちプラザにて開催されたスマートインフォメディアシステム(SIS)研究会にて筒井(助教)が研究成果を発表しました． 前野 達生, 筒井 弘, 尾上 孝雄, “動き検出履歴とコスト最適化に基づくデインタレース手法に関する検討”, 電子情報通信学会技術研究報告, Vol.112, No.78, SIS2012-15, pp.77-82, 2012年6月.
Posted in Conference/Workshop
Tagged IEICE, 研究会
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DAC 2012 (06/03-07)
Sorry, this entry is only available in 中文 and 日本語.
IEEE VTS’12 (04/23-26)
2012年4月23日〜26日に，アメリカ合衆国・ハワイ州，Hyatt Mauiにて IEEE VTS’12 (30th VLSI Test Symposium) が開催され，D2 新谷が発表を行いました． Michihiro Shintani and Takashi Sato, “A Bayesian-based process parameter estimation using IDDQ current signature,” IEEE VLSI test symposium (VTS), pp.86-91, April, 2012.
ISQED2012 (03/19-03/21)
2012年3月19日〜21日に，アメリカ合衆国・カリフォルニア州Santa Clara，Techmart Centerにて開催された ISQED (The International Symposium on Quality Electronic Design) Symposium 2012 で，佐藤が研究成果の発表を行いました． Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, and Hiroyuki Ochi: “Statistical Observations of NBTI-Induced Threshold Voltage Shifts on Small Channel-Area Devices,” in Proc. of International … Continue reading
TAU’12 (01/18-01/20)
2012年1月18日〜20日に，台湾・台北市，National Taiwan Universityにて TAU ’12 Workshop (The 19th ACM/IEEE International Workshop o Timing Issues in the Specification and Synthesis of Digital Systems) が開催され，M2 湯浅が発表を行いました． Hiroshi Yuasa, et.al., “Acceleration Scheme for Monte Carlo based SSTA using Generalized STA Processing Element”
参加学会2011年
2011年03月14日～03月16日に，アメリカ合衆国・カリフォルニア州Santa Clara，Hyatt Regency HotelにてISQED(The International Symposium on Quality Electronic Design) Symposium 2011が開催され，M1(当時)の湯浅君が発表を行いました． Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, and Takashi Sato: “A Fully Pipelined Implementation of Monte Carlo Based SSTA on FPGAs,” in Proc. of International Symposium on Quality Electrical … Continue reading