Category Archives: Publication

DATE 2017

Posted on Tuesday April 4th, 2017 by hiromoto

Mr. Song Bian presented his paper at Design, Automation and Test  in Europe (DATE) 2017 held in Lausanne, Switzerland. The acceptance rate of oral presentation is 24%. Song’s talk was on the realization of a secured content addressable memory (CAM) … Continue reading →

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APEC 2017

Posted on Tuesday April 4th, 2017 by hiromoto

Dr. Shintani presented his paper at IEEE Applied Power Electronics Conference and Exposition (APEC) 2017 held in Tampa, FL, USA. Dr. Shintani’s presentation was a pioneer work on the security of power devices. APEC is the leading conference in the … Continue reading →

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ICMTS 2017

Posted on Tuesday April 4th, 2017 by ts

Mr. Oishi presented his paper at International Conference on Microelectronic Test Structures (ICMTS) 2017 held in Grenoble, France. Mr. Oishi’s talk was about input capacitance measurement of power MOSFETs. The modeling of the input capacitance is crucial for the simulation … Continue reading →

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(日本語) 2017年 電子情報通信学会 総合大会

Posted on Tuesday April 4th, 2017 by hiromoto

Sorry, this entry is only available in 日本語.

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ISQED 2017

Posted on Tuesday March 28th, 2017 by hiromoto

Mr. Morita presented his paper at International Symposium on Quality Electronic Design (ISQED) 2017 held in Santa Clara, CA. Mr. Morita’s talk was about the mitigation of the circuit degradation. Replacement of highly stressed logic gates with internal node control … Continue reading →

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(日本語) 第30回 回路とシステムワークショップ 採択決定

Posted on Thursday March 16th, 2017 by hiromoto

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(日本語) 2017年3月SIS研究会

Posted on Tuesday March 7th, 2017 by hiromoto

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Student paper accepted for publication in IEICE journal

Posted on Tuesday February 28th, 2017 by hiromoto

Following paper written by M1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “Utilization of Path-Clustering in Efficient Stress-Control Gate … Continue reading →

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Student paper accepted for presentation in DAC 2017

Posted on Monday February 13th, 2017 by hiromoto

The following paper has been accepted for presentation in DAC 2017 (ACM/IEEE Design Automation Conference). Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations,” in Proc. of ACM/IEEE Design Automation … Continue reading →

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ACM/IEEE ASPDAC 2017

Posted on Wednesday January 25th, 2017 by ts

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