Category Archives: Publication

Student paper accepted for presentation in CVPRW 2016

Posted on Thursday April 28th, 2016 by hiromoto

The following paper has been accepted for presentation in CVPRW/EVW2016 (IEEE Conference on Computer Vision and Pattern Recognition Workshops/The Twelfth IEEE Embedded Vision Workshop）. Takayuki Ujiie, Masayuki Hiromoto, and Takashi Sato: “Approximated Prediction Strategy for Reducing Power Consumption of Convolutional … Continue reading →

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(日本語) TAU 2016

Posted on Friday April 1st, 2016 by hiromoto

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(日本語) ISQED 2016

Posted on Wednesday March 23rd, 2016 by hiromoto

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(日本語) 2016年 電子情報通信学会 総合大会

Posted on Wednesday March 23rd, 2016 by hiromoto

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(日本語) 平成28年 電気学会全国大会

Posted on Monday March 21st, 2016 by hiromoto

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(日本語) 第29回 回路とシステムワークショップ 採択決定

Posted on Monday March 21st, 2016 by hiromoto

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(日本語) 2016年3月VLD研究会

Posted on Monday March 7th, 2016 by hiromoto

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Student papers accepted for publication in IEICE journal

Posted on Saturday March 5th, 2016 by hiromoto

Following papers written by students (D3 and M1) have been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter … Continue reading →

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Student paper accepted for presentation in DAC 2016

Posted on Thursday February 18th, 2016 by hiromoto

The following paper has been accepted for presentation in DAC 2016 (ACM/IEEE Design Automation Conference). Hiromitsu Awano and Takashi Sato, “Efficient Transistor-level Timing Yield Estimation via Line Sampling,” ACM/IEEE Design Automation Conference (DAC), accepted for presentation, Jun 2016. (Austin, TX)

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Student paper accepted for presentation in GLSVLSI 2016

Posted on Wednesday February 17th, 2016 by hiromoto

A paper is accepted for presentation in GLSVLSI 2016 (Boston, MA). Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation,” Great Lakes Symposium on VLSI (GLSVLSI) (Boston, MA), … Continue reading →

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