Author Archives: ts

A paper has been accepted for publication in IEEE Transactions on Device and Materials Reliability

Posted on Monday March 3rd, 2014 by ts

Sorry, this entry is only available in 日本語.

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(日本語) 第26回 回路とシステムワークショップ 奨励賞 受賞

Posted on Tuesday February 18th, 2014 by ts
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(日本語) 3回生(研究室配属対象者)向け研究室見学会

Posted on Sunday February 16th, 2014 by ts

Sorry, this entry is only available in 日本語.

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(日本語) 電子情報通信学会 ディペンダブルコンピューティング研究会(DC)

Posted on Thursday February 13th, 2014 by ts
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Our paper has been accepted for publication in IEEE Trans. on CAD

Posted on Tuesday January 21st, 2014 by ts

The following paper has been accepted for publication in IEICE Transactions on Electronics. Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, and Takashi Sato, “A Variability-Aware Adaptive Test Flow for Test Quality Improvement,” to appear in … Continue reading →

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A paper has been accepted for publication in IEICE Transactions

Posted on Monday January 6th, 2014 by ts

The following paper has been accepted for publication in IEICE Transactions on Electronics. Shiho Hagiwara, Takanori Date, Kazuya Masu, and Takashi Sato, “Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis,” to appear in IEICE Transactions on Electronics.

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A journal paper has been published on Trans. IEICE

Posted on Wednesday January 1st, 2014 by ts

The following paper has been published on the January issue of Trans. IEICE(Kyoto University repository). This was a joint work with Murata Manufacturing, Co. Ltd., Tokyo Institute of Technology, and our group in Kyoto University.  Koh Yamanaga, Shiho Hagiwara, Ryo … Continue reading →

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Stanford d.school

Posted on Tuesday December 3rd, 2013 by ts

After the VMC2013 workshop, Sato visited the d.school at Stanford University. After the VMC2013 workshop, Sato visited the d.school at Stanford University.

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VMC2013

Posted on Friday November 29th, 2013 by ts

On Nov. 21, Mr. Awano presented his recent work on long term reliability of VLSI circuits at VMC2013 held in San Jose. Bias temperature instability (BTI) is considered to have significant impact on long term reliability of VLSI.  At the … Continue reading →

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ASICON 2013

Posted on Monday November 4th, 2013 by ts

Prof. Sato gave a talk in ASICON 2013, which is held on Oct.28-31, 2013, in Shenzhen, China. Takashi Sato, “Statistical simulation methods for analyzing performance of low supply voltage circuits (invited),” in Proc. IEEE 10th International Conference on ASIC (ASICON), … Continue reading →

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