Author Archives: admin

Design Gaia 2015

Posted on Wednesday December 9th, 2015 by admin

At Design Gaia 2015, held in Nagasaki, Awano presented his recent research work. IEEE CEDA All Japan Joint Chapter Design Gaia Best Poster Award was given on his poster presentation. 粟野 皓光，佐藤 高史: モンテカルロ法に基づくタイミング歩留り解析の高速化, 電子情報通信学会技術研究報告（デザインガイア2015）, VLD2015-16, 長崎県勤労福祉会館, 2015年12月．

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(日本語) VMC2015

Posted on Wednesday November 18th, 2015 by admin

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(日本語) VDECデザイナーズフォーラム2015

Posted on Tuesday September 1st, 2015 by admin

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(日本語) IEEE Student Branch Leadership Training Workshop

Posted on Thursday May 21st, 2015 by admin

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(日本語) 研究室歓送会 2015

Posted on Tuesday March 24th, 2015 by admin
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DATE2015

Posted on Tuesday March 17th, 2015 by admin

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(日本語) 第11回IEEE関西支部学生研究奨励賞 受賞

Posted on Friday February 13th, 2015 by admin

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(日本語) 2015年1月EMCJ研究会

Posted on Tuesday February 3rd, 2015 by admin

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(日本語) 2014年度 忘年会

Posted on Thursday December 25th, 2014 by admin

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(日本語) デザインガイア2014

Posted on Monday December 1st, 2014 by admin

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