Author Archives: hiromoto

(日本語) 電気学会 電子デバイス・半導体電力変換合同研究会 学生奨励賞を受賞

Posted on Sunday December 10th, 2017 by hiromoto

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Student paper accepted for presentation in ISQED 2018

Posted on Thursday December 7th, 2017 by hiromoto

The following paper has been accepted for presentation in ISQED 2018 (International Symposium on Quality Electronic Design). Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “A Study on NBTI-Induced Delay Degradation Considering Stress Frequency Dependence,” in … Continue reading →

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Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Posted on Monday December 4th, 2017 by hiromoto

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms … Continue reading →

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Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Posted on Monday December 4th, 2017 by hiromoto

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. A circuit-aging simulation that efficiently calculates temporal change of rare circuit-failure probability is proposed. While conventional methods required a long computational time due … Continue reading →

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(日本語) 電気学会 半導体電力変換(SPC)研究会

Posted on Friday November 24th, 2017 by hiromoto

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Paper accepted for publication in Japanese Journal of Applied Physics

Posted on Friday November 17th, 2017 by hiromoto

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). Michihiro Shintani, Zhaoxing Qin, Kazunori Kuribara, Yasuhiro Ogasahara, Masayuki Hiromoto, and Takashi Sato: “Mechanically and Electrically Robust Metal-Mask Design for Organic CMOS Circuits,” Japanese Journal … Continue reading →

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(日本語) 電子情報通信学会 シリコン材料・デバイス(SDM)研究会

Posted on Wednesday November 15th, 2017 by hiromoto

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(日本語) デザインガイア2017

Posted on Monday November 13th, 2017 by hiromoto

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Student paper accepted for publication in IEICE journal

Posted on Monday October 30th, 2017 by hiromoto

Following paper written by M2 student has been accepted for publication in IEICE Transactions on Information and Systems. Hidenori Gyoten, Masayuki Hiromoto, and Takashi Sato: “Area Efficient Annealing Processor for Ising Model without Random Number Generator,” IEICE Transactions on Information and … Continue reading →

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(日本語) 2017年 電子情報通信学会 ソサイエティ大会

Posted on Tuesday September 19th, 2017 by hiromoto

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