Author Archives: hiromoto

Graduation Ceremony

Posted on Tuesday April 4th, 2017 by hiromoto

Graduation Ceremony was held at Miyako-Messe (Kyoto International Exhibition Hall). hat toss!

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Degree conferment ceremony

Posted on Tuesday April 4th, 2017 by hiromoto

Degree conferment ceremony for masters has been held at Miyako-Messe (Kyoto International Exhibition Hall).

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Farewell party 2017

Posted on Tuesday April 4th, 2017 by hiromoto

Pictures at the farewell party.

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ISQED 2017

Posted on Tuesday March 28th, 2017 by hiromoto

Mr. Morita presented his paper at International Symposium on Quality Electronic Design (ISQED) 2017 held in Santa Clara, CA. Mr. Morita’s talk was about the mitigation of the circuit degradation. Replacement of highly stressed logic gates with internal node control … Continue reading →

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(日本語) 第30回 回路とシステムワークショップ 採択決定

Posted on Thursday March 16th, 2017 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) 2017年3月SIS研究会

Posted on Tuesday March 7th, 2017 by hiromoto

Sorry, this entry is only available in 日本語.

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Student paper accepted for publication in IEICE journal

Posted on Tuesday February 28th, 2017 by hiromoto

Following paper written by M1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “Utilization of Path-Clustering in Efficient Stress-Control Gate … Continue reading →

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(日本語) 第13回IEEE関西支部学生研究奨励賞 受賞

Posted on Sunday February 26th, 2017 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) IEEE PELS Japan Young Engineer Award 受賞

Posted on Monday February 20th, 2017 by hiromoto

Sorry, this entry is only available in 日本語.

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Lab tour for EE students

Posted on Monday February 20th, 2017 by hiromoto

Lab tour for prospective senior students in EE has been held on Feb. 20, 2017.  Students who are interested in joining our group but missed the lab tour, contact us via e-mail.

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