Author Archives: hiromoto

(日本語) 2016年 電子情報通信学会 総合大会

Posted on Wednesday March 23rd, 2016 by hiromoto

Sorry, this entry is only available in 日本語.

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(日本語) 平成28年 電気学会全国大会

Posted on Monday March 21st, 2016 by hiromoto

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(日本語) 第29回 回路とシステムワークショップ 採択決定

Posted on Monday March 21st, 2016 by hiromoto

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IPSJ Yamashita SIG Research Award

Posted on Wednesday March 16th, 2016 by hiromoto

H. Awano received the “IPSJ Yamashita SIG Research Award” on the following paper. 粟野 皓光, 廣本 正之, 佐藤 高史: “3996トランジスタにおけるNBTI劣化の統計的ばらつき”, 情報処理学会DAシンポジウム2014 (於 岐阜県下呂市 ホテル下呂温泉水明館), pp.3-8, 2014年8月.

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AR.Drone contest 2016

Posted on Friday March 11th, 2016 by hiromoto

The 3rd AR.Drone contest was held on March 8th at Kyoto Research Park. This event is a part of the Spring Design School held by “Collaborative Graduate Program in Design”.  The objective of the contest is to develop a program … Continue reading →

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(日本語) 2016年3月VLD研究会

Posted on Monday March 7th, 2016 by hiromoto

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Student papers accepted for publication in IEICE journal

Posted on Saturday March 5th, 2016 by hiromoto

Following papers written by students (D3 and M1) have been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter … Continue reading →

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Lab tour for EE students

Posted on Thursday February 25th, 2016 by hiromoto

Lab tour for prospective senior students in EE has been held on Feb. 24, 2016.  Students who are interested in joining our group but missed the lab tour, contact us via e-mail.

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Student paper accepted for presentation in DAC 2016

Posted on Thursday February 18th, 2016 by hiromoto

The following paper has been accepted for presentation in DAC 2016 (ACM/IEEE Design Automation Conference). Hiromitsu Awano and Takashi Sato, “Efficient Transistor-level Timing Yield Estimation via Line Sampling,” ACM/IEEE Design Automation Conference (DAC), accepted for presentation, Jun 2016. (Austin, TX)

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Student paper accepted for presentation in GLSVLSI 2016

Posted on Wednesday February 17th, 2016 by hiromoto

A paper is accepted for presentation in GLSVLSI 2016 (Boston, MA). Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation,” Great Lakes Symposium on VLSI (GLSVLSI) (Boston, MA), … Continue reading →

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