Tag Archives: Journal

Paper accepted for publication in Japanese Journal of Applied Physics

Posted on Friday November 17th, 2017 by hiromoto

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). Michihiro Shintani, Zhaoxing Qin, Kazunori Kuribara, Yasuhiro Ogasahara, Masayuki Hiromoto, and Takashi Sato: “Mechanically and Electrically Robust Metal-Mask Design for Organic CMOS Circuits,” Japanese Journal … Continue reading →

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Student paper accepted for publication in IEICE journal

Posted on Monday October 30th, 2017 by hiromoto

Following paper written by M2 student has been accepted for publication in IEICE Transactions on Information and Systems. Hidenori Gyoten, Masayuki Hiromoto, and Takashi Sato: “Area Efficient Annealing Processor for Ising Model without Random Number Generator,” IEICE Transactions on Information and … Continue reading →

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Student paper accepted for publication in IEICE journal

Posted on Thursday August 17th, 2017 by hiromoto

Following paper written by D1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato: “Identification and Application of Invariant … Continue reading →

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Paper published in IEEE Trans. VLSI

Posted on Tuesday August 1st, 2017 by ts

Sorry, this entry is only available in 日本語.

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Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Posted on Wednesday July 19th, 2017 by hiromoto

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation … Continue reading →

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Paper accepted for publication in IEEE Transactions on Biomedical Engineering

Posted on Sunday April 16th, 2017 by hiromoto

The following paper has been accepted for publication in IEEE Transactions on Biomedical Engineering (TBME). Yuya Fujita, Masayuki Hiromoto, and Takashi Sato: “PARHELIA: Particle Filter-Based Heart Rate Estimation from Photoplethysmographic Signals During Physical Exercise,” IEEE Transactions on Biomedical Engineering, 2017. … Continue reading →

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Student paper accepted for publication in IEICE journal

Posted on Tuesday February 28th, 2017 by hiromoto

Following paper written by M1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “Utilization of Path-Clustering in Efficient Stress-Control Gate … Continue reading →

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Paper accepted for publication in IEEE Transactions on Very Large Scale Integration Systems

Posted on Thursday January 5th, 2017 by ts

The following paper has been accepted for publication in IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Hiromitsu Awano, Shumpei Morita, and Takashi Sato: “Scalable device array for statistical characterization of BTI-related parameters,” IEEE Transactions on Very Large Scale … Continue reading →

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Paper accepted for publication in Japanese Journal of Applied Physics

Posted on Monday December 19th, 2016 by hiromoto

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). Michihiro Shintani, Yohei Nakamura, Masayuki Hiromoto, Takashi Hikihara, and Takashi Sato: “Measurement and Modeling on Gate-Drain Capacitance of Silicon Carbide Vertical MOSFET,” Japanese Journal of … Continue reading →

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Paper accepted for publication in Journal of Electronic Testing: Theory and Applications

Posted on Wednesday August 24th, 2016 by hiromoto

Following paper has been accepted for publication in Journal of Electronic Testing: Theory and Applications (JETTA). Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, and Takashi Sato: “Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing,” Journal … Continue reading →

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