Tag Archives: DAC
The following paper has been accepted for presentation in DAC2019（ACM/IEEE Design Automation Conference 2019） (acceptance rate 24.8%=202/815). Conguratulations!! Song Bian, Masayuki Hiromoto, and Takashi Sato, “Filianore: Better multiplier architectures for LWE-based post-quantum key exchange,” in Proc. ACM/IEEE Design Automation Conference … Continue reading
Mr. Song Bian presented his paper in Design Automation Conference (DAC) 2017 held in Austin, Tx. Song’s presentation was on creating learning-based STA libraries for characterizing aging-induced device variations. Traditional approach to the accurate characterization of aging (specifically negative bias … Continue reading
The following paper has been accepted for presentation in DAC 2017 (ACM/IEEE Design Automation Conference). Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato: “LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations,” in Proc. of ACM/IEEE Design Automation … Continue reading
Nikkei BP online now uploaded a tutorial article on our DAC2016 paper.
Dr. Awano presented a paper in Design Automation Conference (DAC) 2016 held in Austin, Tx. His talk is about the accelerated calculation of timing yield of logic circuits. By introducing the idea of Line sampling to the timing analysis, simulations … Continue reading
The following paper has been accepted for presentation in DAC 2016 (ACM/IEEE Design Automation Conference). Hiromitsu Awano and Takashi Sato, “Efficient Transistor-level Timing Yield Estimation via Line Sampling,” ACM/IEEE Design Automation Conference (DAC), accepted for presentation, Jun 2016. (Austin, TX)