Following paper written by D1 student has been accepted for publication in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
- Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato:
“Identification and Application of Invariant Critical Paths under NBTI Degradation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Dec. 2017 (to appear).
Kyoto University open campus was held on Aug. 9 and 10. As a part of the open campus, we hosted lab tours for high school students.
Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.
- Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
“Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.7, pp.1464-1472, July 2017.
The following paper has been accepted for oral presentation in International Conference on Solid State Devices and Materials (SSDM), which will be held during September 19-22, 2017.
- Michihiro Shintani, Kazunori Kuribara, Yasuhiro Ogasahara, Masayuki Hiromoto, and Takashi Sato:
“A Design-Analysis Flow Considering Mechanical Stability of Metal Masks for Organic CMOS Circuits,” in Proc. of International Conference on Solid Devices and Materials (SSDM) (Sendai, Japan), Sep. 2017 (to appear).
Mr. Song Bian presented his paper in Design Automation Conference (DAC) 2017 held in Austin, Tx.
Song’s presentation was on creating learning-based STA libraries for characterizing aging-induced device variations. Traditional approach to the accurate characterization of aging (specifically negative bias temperature instability (NBTI) studied in this work) is to build an interpolation-based high-dimensional library which is prohibitive in library creation time. In this work, we proposed a regression-based learning approach to the making of STA library. In our approach, a learning algorithm will be optimized to learn the relationship between aging-induced variations and aged delay, where the aged delays are given as correct training data. The optimized algorithm will then be used as the STA library to predict the delay of gates in test designs. Through experiment, we achieved an maximum absolute error of less than 4%, demonstrating that accurate STA can be carried out without the need of high-dimensional interpolation.
DAC is the largest and most prestigious conference in this area. A large number of attendees gather to the conference which is held in conjunction with a huge exhibition and collocated workshops.
- Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
“LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations,” in Proc. of ACM/IEEE Design Automation Conference (DAC), 73.3, June 2017.