Paper Published on IEEE Transactions on Biomedical Engineering

The following paper has been published on IEEE Transactions on Biomedical Engineering.

The photoplethysmographic (PPG) signal is an important source of information for estimating heart rate (HR). However, the PPG signal could be strongly contaminated by the motion artifact of the subjects, making HR estimation a particularly difficult problem. In this paper, we propose PARHELIA, a PARticle filter-based algorithm for HEart rate estimation using photopLethysmographIc signAls. The proposed method employs a particle filter, and utilizes the simultaneously recorded acceleration signals from a wrist-type sensor, to keep track of multiple HR candidates. This achieves quick recovery from incorrect HR estimations under the strong influence of the MA. Experimental results for a dataset of 12 subjects recorded during fast running showed that the average absolute estimation error was 1.17 beats per minute (BPM) whereas that of the best-known conventional method, JOSS, is 1.28 BPM. Furthermore, the estimation time of PARHELIA is 20 times shorter than JOSS.

  • Yuya Fujita, Masayuki Hiromoto, and Takashi Sato:
    “PARHELIA: Particle Filter-Based Heart Rate Estimation from Photoplethysmographic Signals During Physical Exercise,” IEEE Transactions on Biomedical Engineering, Vol.65, No.1, pp.189-198, Jan. 2018.
    DOI: 10.1109/TBME.2017.2697911
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Lecture talk of Dr. Chun-Wei Lin

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(日本語) 電気学会 電子デバイス・半導体電力変換合同研究会 学生奨励賞を受賞

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Student paper accepted for presentation in ISQED 2018

The following paper has been accepted for presentation in ISQED 2018 (International Symposium on Quality Electronic Design).

  • Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, and Takashi Sato:
    “A Study on NBTI-Induced Delay Degradation Considering Stress Frequency Dependence,” in Proc. of International Symposium on Quality Electronic Design (ISQED) (Santa Clara, CA), Mar. 2018 (to appear).
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Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.

  • Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, and Takashi Sato:
    “Identification and Application of Invariant Critical Paths under NBTI Degradation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, pp.2797-2806, Dec. 2017.
    DOI: 10.1587/transfun.E100.A.2797
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Paper Published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

The following paper has been published on IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.

A circuit-aging simulation that efficiently calculates temporal change of rare circuit-failure probability is proposed. While conventional methods required a long computational time due to the necessity of conducting separate calculations of failure probability at each device age, the proposed Monte Carlo based method requires to run only a single set of simulation. By applying the augmented reliability and subset simulation framework, the change of failure probability along the lifetime of the device can be evaluated through the analysis of the Monte Carlo samples. Combined with the two-step sample generation technique, the proposed method reduces the computational time to about 1/6 of that of the conventional method while maintaining a sufficient estimation accuracy.

  • Hiromitsu Awano and Takashi Sato:
    “Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E100-A, No.12, pp.2807-2815, Dec. 2017.
    DOI: 10.1587/transfun.E100.A.2807
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(日本語) 電気学会 半導体電力変換(SPC)研究会

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VMC2017

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Paper accepted for publication in Japanese Journal of Applied Physics

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP).

  • Michihiro Shintani, Zhaoxing Qin, Kazunori Kuribara, Yasuhiro Ogasahara, Masayuki Hiromoto, and Takashi Sato:
    “Mechanically and Electrically Robust Metal-Mask Design for Organic CMOS Circuits,” Japanese Journal of Applied Physics, Vol.57, No.4S, Apr. 2018 (to appear).
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(日本語) 電子情報通信学会 シリコン材料・デバイス(SDM)研究会

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