Dr. Shintani presented his paper at International Conference on Solid State Devices and Materials (SSDM) held in Tsukuba, Japan.

Dr. Shintani’s talk was about a circuit simulation model for SiC power MOSFET. Circuit simulation models standarized in the industry assume lateral MOSFET structure that has gate, drain, and source terminals on the topside. However, vertical MOSFET structure, whose drain terminal is on the bottom side, is widely used for high power applications. In this work, we proposed a circuit simulation model for vertical SiC power MOSFETs, and demonstrated the effectiveness of the model. This work is a collaborative research with Takashi Hikihara Laboratory, Department of Electrical Engineering, Kyoto University.

  • Michihiro Shintani, Yohei Nakamura, Masayuki Hiromoto, Takashi Hikihara, and Takashi Sato:
    “A Surface-Potential-Based Reverse-Transfer Capacitance Model for Vertical SiC DMOSFET,” in Proc. of International Conference on Solid Devices and Materials (SSDM), PS-14-08, pp.993-994, Sep. 2016.
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