Professor Anupam Chattopadhyay visited our group on May 24.
He gave a seminar talk at the Building 3, Faculty of Engineering, Kyoto University.
Speaker: Prof. Anupam Chattopadhyay
Subject: Future-proof IP Design for Heterogeneous MPSoC
Summary: Heterogeneous Multi-Processor System-on-Chip has become commonplace in diverse application domains to balance the conflicting performance constraints. Within the context of constituent IPs of a heterogeneous MPSoC, we will present two major challenges. Both the challenges are linked with fundamental advances of semiconductor technology and its approaching roadblock at deep submicron technology. First, in the /What /challenge we will discuss about the IPs that one can design for catering to a growing clientele for a long time and still guarantee efficiency. Examples from wireless receiver and cryptography will be discussed in this part. In the second part, the /How /challenge will deal with the ability to design these IPs by considering multiple performance constraints simultaneously. The proposed solutions are based on the Synopsys Processor Designer toolsuite, making these readily available to wide range of users.
Speaker bios: Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India in 2000. He received his MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2002 and 2008 respectively. During his PhD, he worked on automatic RTL generation from the architecture description language LISA, which was commercialized later by CoWare (now part of Synopsys). He further developed several high-level optimizations and verification flow for embedded processors. In his doctoral thesis, he proposed a language-based modeling, exploration and implementation framework for partially re-configurable processors. He has published more than 40 technical papers, authored one book and several book-chapters in the above research areas.
Prof. Dr.-Ing. Chattopadhyay spent over 3 years in various engineering and research positions at industry. In his most recent industrial position he was serving as a Member of Consulting Staff at CoWare, India, where he was responsible for enhancing the quality and capability of a high-level processor synthesis toolsuite.
In 2010, Prof. Dr.-Ing. Chattopadhyay joined RWTH Aachen University as an assistant professor in the UMIC research cluster. He is heading the research group of MPSoC Architectures.